From: Matthew Wilcox <matthew@wil.cx>
To: Christoph Hellwig <hch@infradead.org>
Cc: Hannes Reinecke <hare@suse.de>,
James Bottomley <James.Bottomley@steeleye.com>,
SCSI Mailing List <linux-scsi@vger.kernel.org>
Subject: Re: [PATCH 2/3] aic79xx: Update to adaptec version 2.0.14
Date: Mon, 16 Jan 2006 05:39:10 -0700 [thread overview]
Message-ID: <20060116123910.GA19769@parisc-linux.org> (raw)
In-Reply-To: <20060116120517.GB12554@infradead.org>
On Mon, Jan 16, 2006 at 12:05:17PM +0000, Christoph Hellwig wrote:
> > - *maddr = ioremap_nocache(base_page, base_offset + 256);
> > + *maddr = ioremap_nocache(base_page, base_offset + 512);
>
> so how could this work before?
In the absence of chip documentation, maybe the registers are mapped
several times over, once at +0, once at +256, once at +512, each time with
slightly different semantics? We definitely have chips with register
files in IO space, Mem space and Config space, so choosing to map the
registers several times in the same address space probably just doesn't
seem terribly crazy to hardware people ;-)
Are Adaptec planning on releasing chip documentation?
prev parent reply other threads:[~2006-01-16 12:39 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-01-16 10:03 [PATCH 2/3] aic79xx: Update to adaptec version 2.0.14 Hannes Reinecke
2006-01-16 12:05 ` Christoph Hellwig
2006-01-16 12:39 ` Matthew Wilcox [this message]
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