From mboxrd@z Thu Jan 1 00:00:00 1970
From: bugzilla-daemon@bugzilla.kernel.org
Subject: [Bug 25192] 3w-{9,x}xxx don't work on big-endian MIPS
Date: Sun, 19 Dec 2010 18:04:36 GMT
Message-ID: <201012191804.oBJI4aL7008316@demeter2.kernel.org>
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https://bugzilla.kernel.org/show_bug.cgi?id=25192
--- Comment #7 from ralf@linux-mips.org 2010-12-19 18:04:31 ---
64-bit PCI slots on the Sibyte evaluation boards are implemented using a
Hypertransport-to-PCI bridge. Hypertransport however uses a separate port
address space from the native 32-bit PCI slots that port x on 32-bit PCI is
different from port x on the Hypertransport. Memory mapped I/O is not affected
by the issue.
The in/out functions don't know which of the busses / port address spaces
they're operating on so they're always using the first bus that is the 32-bit
PCI bus. Note that the new style API with iomap() / ioreadX() / iowriteX() is
not affected by this problem.
Would that explain the bug?
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