From: Christoph Hellwig <hch@lst.de>
To: Hannes Reinecke <hare@suse.de>
Cc: "Martin K. Petersen" <martin.petersen@oracle.com>,
Christoph Hellwig <hch@lst.de>,
James Bottomley <james.bottomley@hansenpartnership.com>,
Sathya Prakash <sathya.prakash@broadcom.com>,
linux-scsi@vger.kernel.org, Hannes Reinecke <hare@suse.com>
Subject: Re: [PATCH] mpt3sas: switch to pci_alloc_irq_vectors
Date: Fri, 2 Dec 2016 15:30:37 +0100 [thread overview]
Message-ID: <20161202143036.GB31264@lst.de> (raw)
In-Reply-To: <1480679607-79306-1-git-send-email-hare@suse.de>
> +static inline u16
> _base_get_msix_index(struct MPT3SAS_ADAPTER *ioc)
> {
> + return pci_irq_get_affinity_vector(ioc->pdev, raw_smp_processor_id());
> }
This looks extremely sketchy. Are we guaranteed to always have enough
MSI-X vectors that each CPU has it's own? I'd much prefer to keep the
indirection array of the existing code.
> +static int scsih_map_queues(struct Scsi_Host *shost)
> +{
> + struct MPT3SAS_ADAPTER *ioc = shost_priv(shost);
> +
> + return blk_mq_pci_map_queues(&shost->tag_set, ioc->pdev, 0);
> +}
Given that mpt3sas only supports a single hardware queue (and doesn't
set the nr_hw_queues field) this is pointless and won't have any effect.
next prev parent reply other threads:[~2016-12-02 14:30 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-02 11:53 [PATCH] mpt3sas: switch to pci_alloc_irq_vectors Hannes Reinecke
2016-12-02 14:30 ` Christoph Hellwig [this message]
2016-12-02 14:45 ` Hannes Reinecke
2016-12-03 2:01 ` kbuild test robot
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