From: <peter.wang@mediatek.com>
To: <chun-hung.wu@mediatek.com>, <linux-scsi@vger.kernel.org>,
<martin.petersen@oracle.com>, <avri.altman@wdc.com>,
<alim.akhtar@samsung.com>, <jejb@linux.ibm.com>
Cc: <wsd_upstream@mediatek.com>, <linux-mediatek@lists.infradead.org>,
<peter.wang@mediatek.com>, <alice.chao@mediatek.com>,
<cc.chou@mediatek.com>, <chaotian.jing@mediatek.com>,
<jiajie.hao@mediatek.com>, <powen.kao@mediatek.com>,
<qilin.tan@mediatek.com>, <lin.gui@mediatek.com>,
<tun-yu.yu@mediatek.com>, <eddie.huang@mediatek.com>,
<naomi.chu@mediatek.com>, <chu.stanley@gmail.com>
Subject: [PATCH v1 3/3] ufs: host: mediatek: disable mcq irq when clock off
Date: Thu, 21 Dec 2023 19:04:16 +0800 [thread overview]
Message-ID: <20231221110416.16176-4-peter.wang@mediatek.com> (raw)
In-Reply-To: <20231221110416.16176-1-peter.wang@mediatek.com>
From: Peter Wang <peter.wang@mediatek.com>
Disable mcq irq when clock off, this is same as legacy mode.
Signed-off-by: Peter Wang <peter.wang@mediatek.com>
---
drivers/ufs/host/ufs-mediatek.c | 41 +++++++++++++++++++++++++++++++++
drivers/ufs/host/ufs-mediatek.h | 1 +
2 files changed, 42 insertions(+)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index eb1934126c87..51f05038408a 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -660,6 +660,45 @@ static void ufs_mtk_pwr_ctrl(struct ufs_hba *hba, bool on)
}
}
+static void ufs_mtk_mcq_disable_irq(struct ufs_hba *hba)
+{
+ struct ufs_mtk_host *host = ufshcd_get_variant(hba);
+ u32 irq, i;
+
+ if (!is_mcq_enabled(hba))
+ return;
+
+ if (host->mcq_nr_intr == 0)
+ return;
+
+ for (i = 0; i < host->mcq_nr_intr; i++) {
+ irq = host->mcq_intr_info[i].irq;
+ disable_irq(irq);
+ }
+ host->is_mcq_intr_enabled = false;
+}
+
+static void ufs_mtk_mcq_enable_irq(struct ufs_hba *hba)
+{
+ struct ufs_mtk_host *host = ufshcd_get_variant(hba);
+ u32 irq, i;
+
+ if (!is_mcq_enabled(hba))
+ return;
+
+ if (host->mcq_nr_intr == 0)
+ return;
+
+ if (host->is_mcq_intr_enabled == true)
+ return;
+
+ for (i = 0; i < host->mcq_nr_intr; i++) {
+ irq = host->mcq_intr_info[i].irq;
+ enable_irq(irq);
+ }
+ host->is_mcq_intr_enabled = true;
+}
+
/**
* ufs_mtk_setup_clocks - enables/disable clocks
* @hba: host controller instance
@@ -703,8 +742,10 @@ static int ufs_mtk_setup_clocks(struct ufs_hba *hba, bool on,
if (clk_pwr_off)
ufs_mtk_pwr_ctrl(hba, false);
+ ufs_mtk_mcq_disable_irq(hba);
} else if (on && status == POST_CHANGE) {
ufs_mtk_pwr_ctrl(hba, true);
+ ufs_mtk_mcq_enable_irq(hba);
}
return ret;
diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h
index f76e80d91729..922f1e51a60c 100644
--- a/drivers/ufs/host/ufs-mediatek.h
+++ b/drivers/ufs/host/ufs-mediatek.h
@@ -186,6 +186,7 @@ struct ufs_mtk_host {
u32 ip_ver;
bool mcq_set_intr;
+ bool is_mcq_intr_enabled;
int mcq_nr_intr;
struct ufs_mtk_mcq_intr_info mcq_intr_info[UFSHCD_MAX_Q_NR];
};
--
2.18.0
next prev parent reply other threads:[~2023-12-21 11:04 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-21 11:04 [PATCH v1 0/3] ufs: host: mediatek: Provide fixes in MediaTek platforms peter.wang
2023-12-21 11:04 ` [PATCH v1 1/3] ufs: host: mediatek: check link status after exit hibern8 peter.wang
2023-12-25 7:20 ` Chun-Hung Wu (巫駿宏)
2023-12-21 11:04 ` [PATCH v1 2/3] ufs: host: mediatek: fix mcq mode tm cmd timeout peter.wang
2023-12-25 7:20 ` Chun-Hung Wu (巫駿宏)
2023-12-21 11:04 ` peter.wang [this message]
2023-12-25 7:22 ` [PATCH v1 3/3] ufs: host: mediatek: disable mcq irq when clock off Chun-Hung Wu (巫駿宏)
2024-01-24 2:06 ` [PATCH v1 0/3] ufs: host: mediatek: Provide fixes in MediaTek platforms Martin K. Petersen
2024-01-30 2:27 ` Martin K. Petersen
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