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charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <93539579c4eb5bacc9dc9afb726294f44cec7dc9.camel@mediatek.com> On Fri, Jun 21, 2024 at 03:32:18AM +0000, Peter Wang (王信友) wrote: > On Wed, 2024-06-19 at 13:27 +0530, Manivannan Sadhasivam wrote: > > > > --- a/include/ufs/ufshci.h > > > > +++ b/include/ufs/ufshci.h > > > > @@ -67,7 +67,7 @@ enum { > > > > > > > > /* Controller capability masks */ > > > > enum { > > > > -MASK_TRANSFER_REQUESTS_SLOTS= 0x0000001F, > > > > +MASK_TRANSFER_REQUESTS_SLOTS= 0x000000FF, > > > > > > This should be a separate fix that comes before this patch. But I > > believe this > > > came up during MCQ review as well and I don't remember what was the > > reply from > > > Can. 0x1F is the mask for SDB mode and 0xFF is the mask for MCQ > > mode. > > > > > > Can, can you comment more? > > > > > > > Hi Bart and Mani, > > It is correct that 0x1F is SDB mode. > ufshcd_mcq_decide_queue_depth is running before mcq enable. > So that value read is still SDB value, not MCQ value. > I don't quite understand. My concern was that if we change the mask for MCQ, then existing 'nutrs' value for SDB could be impacted with this change. Perhaps we should use different masks? - Mani > > Thanks. > Peter > > > > Oops. Can is not CCed. Added now. > > > > - Mani > > > > > > > - Mani > > > > > > -- > > > மணிவண்ணன் சதாசிவம் > > > > -- > > மணிவண்ணன் சதாசிவம் -- மணிவண்ணன் சதாசிவம்