[PATCH V3 0/3] ufs: ufs-qcom: Align programming sequence as per HW spec

[PATCH V3 0/3] ufs: ufs-qcom: Align programming sequence as per HW spec

[Nitin Rawat]

This patch series adds programming support for Qualcomm UFS
to align with Hardware Specification.

In this patch series below changes are taken care.

1. Enable QUnipro Internal Clock Gating
2. Update esi_vec_mask for HW major version >= 6

Changes from v2:
1. Addressed bart's and Mani's comment to move ufshcd_dme_rmw
   to ufshcd.c
2. Addressed Mani's and bart's comment to avoid initialisation
   of cfg.
3. Addressed Mani's comment to update commit text.

Changes from v1:
1. Moved ufshcd_dme_rmw to ufshcd.h as per avri's comment.

Bao D. Nguyen (1):
  ufs: ufs-qcom: Update esi_vec_mask for HW major version >= 6

Nitin Rawat (2):
  scsi: ufs: core: Add ufshcd_dme_rmw to modify DME attributes
  ufs: ufs-qcom: Enable QUnipro Internal Clock Gating

 drivers/ufs/core/ufshcd.c   | 24 ++++++++++++++++++++++++
 drivers/ufs/host/ufs-qcom.c | 24 ++++++++++++++++++++++--
 drivers/ufs/host/ufs-qcom.h |  9 +++++++++
 include/ufs/ufshcd.h        |  1 +
 4 files changed, 56 insertions(+), 2 deletions(-)

--
2.48.1

[PATCH V3 1/3] ufs: ufs-qcom: Update esi_vec_mask for HW major version >= 6

[Nitin Rawat]

From: "Bao D. Nguyen" <quic_nguyenb@quicinc.com>

The MCQ feature and ESI are supported by all Qualcomm UFS controller
versions 6 and above.

Therefore, update the ESI vector mask in the UFS_MEM_CFG3 register
for platforms with major version number of 6 or higher.

Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Bao D. Nguyen <quic_nguyenb@quicinc.com>
Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
---
 drivers/ufs/host/ufs-qcom.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 318dca7fe3d7..dfdc52333a96 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -2113,8 +2113,7 @@ static int ufs_qcom_config_esi(struct ufs_hba *hba)

 	retain_and_null_ptr(qi);

-	if (host->hw_ver.major == 6 && host->hw_ver.minor == 0 &&
-	    host->hw_ver.step == 0) {
+	if (host->hw_ver.major >= 6) {
 		ufshcd_rmwl(hba, ESI_VEC_MASK, FIELD_PREP(ESI_VEC_MASK, MAX_ESI_VEC - 1),
 			    REG_UFS_CFG3);
 	}
--
2.48.1

[PATCH V3 2/3] scsi: ufs: core: Add ufshcd_dme_rmw to modify DME attributes

[Nitin Rawat]

Introduce `ufshcd_dme_rmw` API to read, modify, and write DME
attributes in UFS host controllers using a mask and value.

Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
---
 drivers/ufs/core/ufshcd.c | 24 ++++++++++++++++++++++++
 include/ufs/ufshcd.h      |  1 +
 2 files changed, 25 insertions(+)

diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
index 13f7e0469141..8964f8912fb2 100644
--- a/drivers/ufs/core/ufshcd.c
+++ b/drivers/ufs/core/ufshcd.c
@@ -4251,6 +4251,30 @@ int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
 }
 EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);

+/**
+ * ufshcd_dme_rmw - get modify set a DME attribute
+ * @hba - per adapter instance
+ * @mask - mask to apply on read value
+ * @val - actual value to write
+ * @attr - dme attribute
+ */
+int ufshcd_dme_rmw(struct ufs_hba *hba, u32 mask,
+		   u32 val, u32 attr)
+{
+	u32 cfg = 0;
+	int err;
+
+	err = ufshcd_dme_get(hba, UIC_ARG_MIB(attr), &cfg);
+	if (err)
+		return err;
+
+	cfg &= ~mask;
+	cfg |= (val & mask);
+
+	return ufshcd_dme_set(hba, UIC_ARG_MIB(attr), cfg);
+}
+EXPORT_SYMBOL_GPL(ufshcd_dme_rmw);
+
 /**
  * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
  * state) and waits for it to take effect.
diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h
index 9b3515cee711..1d3943777584 100644
--- a/include/ufs/ufshcd.h
+++ b/include/ufs/ufshcd.h
@@ -1480,6 +1480,7 @@ void ufshcd_resume_complete(struct device *dev);
 bool ufshcd_is_hba_active(struct ufs_hba *hba);
 void ufshcd_pm_qos_init(struct ufs_hba *hba);
 void ufshcd_pm_qos_exit(struct ufs_hba *hba);
+int ufshcd_dme_rmw(struct ufs_hba *hba, u32 mask, u32 val, u32 attr);

 /* Wrapper functions for safely calling variant operations */
 static inline int ufshcd_vops_init(struct ufs_hba *hba)
--
2.48.1

[PATCH V3 3/3] ufs: ufs-qcom: Enable QUnipro Internal Clock Gating

[Nitin Rawat]

Enable internal clock gating for QUnipro by setting the following
attributes to 1 during host controller initialization:
- DL_VS_CLK_CFG
- PA_VS_CLK_CFG_REG
- DME_VS_CORE_CLK_CTRL.DME_HW_CGC_EN

This change is necessary to support the internal clock gating mechanism
in Qualcomm UFS host controller. This is power saving feature and hence
driver can continue to function correctly despite any error in enabling
these feature.

Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
---
 drivers/ufs/host/ufs-qcom.c | 21 +++++++++++++++++++++
 drivers/ufs/host/ufs-qcom.h |  9 +++++++++
 2 files changed, 30 insertions(+)

diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index dfdc52333a96..4bbe4de1679b 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -558,11 +558,32 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
  */
 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
 {
+	int err;
+
+	/* Enable UTP internal clock gating */
 	ufshcd_rmwl(hba, REG_UFS_CFG2_CGC_EN_ALL, REG_UFS_CFG2_CGC_EN_ALL,
 		    REG_UFS_CFG2);

 	/* Ensure that HW clock gating is enabled before next operations */
 	ufshcd_readl(hba, REG_UFS_CFG2);
+
+	/* Enable Unipro internal clock gating */
+	err = ufshcd_dme_rmw(hba, DL_VS_CLK_CFG_MASK,
+			     DL_VS_CLK_CFG_MASK, DL_VS_CLK_CFG);
+	if (err)
+		goto out;
+
+	err = ufshcd_dme_rmw(hba, PA_VS_CLK_CFG_REG_MASK,
+			     PA_VS_CLK_CFG_REG_MASK, PA_VS_CLK_CFG_REG);
+	if (err)
+		goto out;
+
+	err = ufshcd_dme_rmw(hba, DME_VS_CORE_CLK_CTRL_DME_HW_CGC_EN,
+			     DME_VS_CORE_CLK_CTRL_DME_HW_CGC_EN,
+			     DME_VS_CORE_CLK_CTRL);
+out:
+	if (err)
+		dev_err(hba->dev, "hw clk gating enabled failed\n");
 }

 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
index 0a5cfc2dd4f7..e0e129af7c16 100644
--- a/drivers/ufs/host/ufs-qcom.h
+++ b/drivers/ufs/host/ufs-qcom.h
@@ -24,6 +24,15 @@

 #define UFS_QCOM_LIMIT_HS_RATE		PA_HS_MODE_B

+/* bit and mask definitions for PA_VS_CLK_CFG_REG attribute */
+#define PA_VS_CLK_CFG_REG      0x9004
+#define PA_VS_CLK_CFG_REG_MASK GENMASK(8, 0)
+
+/* bit and mask definitions for DL_VS_CLK_CFG attribute */
+#define DL_VS_CLK_CFG          0xA00B
+#define DL_VS_CLK_CFG_MASK GENMASK(9, 0)
+#define DME_VS_CORE_CLK_CTRL_DME_HW_CGC_EN             BIT(9)
+
 /* QCOM UFS host controller vendor specific registers */
 enum {
 	REG_UFS_SYS1CLK_1US                 = 0xC0,
--
2.48.1

RE: [PATCH V3 3/3] ufs: ufs-qcom: Enable QUnipro Internal Clock Gating

[Avri Altman]

> Enable internal clock gating for QUnipro by setting the following attributes to 1
> during host controller initialization:
> - DL_VS_CLK_CFG
> - PA_VS_CLK_CFG_REG
> - DME_VS_CORE_CLK_CTRL.DME_HW_CGC_EN
> 
> This change is necessary to support the internal clock gating mechanism in
> Qualcomm UFS host controller. This is power saving feature and hence driver
> can continue to function correctly despite any error in enabling these feature.
Does this change offloads clock gating? 
i.e. no need to set UFSHCD_CAP_CLK_GATING ?

Thanks,
Avri

Re: [PATCH V3 2/3] scsi: ufs: core: Add ufshcd_dme_rmw to modify DME attributes

[kernel test robot]

Hi Nitin,

kernel test robot noticed the following build warnings:

[auto build test WARNING on jejb-scsi/for-next]
[also build test WARNING on mkp-scsi/for-next linus/master v6.16-rc5 next-20250708]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Nitin-Rawat/ufs-ufs-qcom-Update-esi_vec_mask-for-HW-major-version-6/20250709-052748
base:   https://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi.git for-next
patch link:    https://lore.kernel.org/r/20250708212534.20910-3-quic_nitirawa%40quicinc.com
patch subject: [PATCH V3 2/3] scsi: ufs: core: Add ufshcd_dme_rmw to modify DME attributes
config: x86_64-buildonly-randconfig-001-20250709 (https://download.01.org/0day-ci/archive/20250709/202507091547.T2t1t8Wz-lkp@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14+deb12u1) 12.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250709/202507091547.T2t1t8Wz-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202507091547.T2t1t8Wz-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> Warning: drivers/ufs/core/ufshcd.c:4262 function parameter 'hba' not described in 'ufshcd_dme_rmw'
>> Warning: drivers/ufs/core/ufshcd.c:4262 function parameter 'mask' not described in 'ufshcd_dme_rmw'
>> Warning: drivers/ufs/core/ufshcd.c:4262 function parameter 'val' not described in 'ufshcd_dme_rmw'
>> Warning: drivers/ufs/core/ufshcd.c:4262 function parameter 'attr' not described in 'ufshcd_dme_rmw'

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH V3 3/3] ufs: ufs-qcom: Enable QUnipro Internal Clock Gating

[Nitin Rawat]

On 7/9/2025 10:46 AM, Avri Altman wrote:
>> Enable internal clock gating for QUnipro by setting the following attributes to 1
>> during host controller initialization:
>> - DL_VS_CLK_CFG
>> - PA_VS_CLK_CFG_REG
>> - DME_VS_CORE_CLK_CTRL.DME_HW_CGC_EN
>>
>> This change is necessary to support the internal clock gating mechanism in
>> Qualcomm UFS host controller. This is power saving feature and hence driver
>> can continue to function correctly despite any error in enabling these feature.
> Does this change offloads clock gating?
> i.e. no need to set UFSHCD_CAP_CLK_GATING ?
No , this change does not offload sw based UFS clock gating. Host 
controller has its own internal clock gating mechanism.
> 
> Thanks,
> Avri

Re: [PATCH V3 3/3] ufs: ufs-qcom: Enable QUnipro Internal Clock Gating

[Konrad Dybcio]

On 7/9/25 11:13 PM, Nitin Rawat wrote:
> 
> 
> On 7/9/2025 10:46 AM, Avri Altman wrote:
>>> Enable internal clock gating for QUnipro by setting the following attributes to 1
>>> during host controller initialization:
>>> - DL_VS_CLK_CFG
>>> - PA_VS_CLK_CFG_REG
>>> - DME_VS_CORE_CLK_CTRL.DME_HW_CGC_EN
>>>
>>> This change is necessary to support the internal clock gating mechanism in
>>> Qualcomm UFS host controller. This is power saving feature and hence driver
>>> can continue to function correctly despite any error in enabling these feature.
>> Does this change offloads clock gating?
>> i.e. no need to set UFSHCD_CAP_CLK_GATING ?
> No , this change does not offload sw based UFS clock gating. Host controller has its own internal clock gating mechanism

Does QUnipro == "the UFS controller found on Qualcomm platforms"?

If so, please use some version of the latter name to make it more
easily discernible 

Konrad

Re: [PATCH V3 3/3] ufs: ufs-qcom: Enable QUnipro Internal Clock Gating

[Nitin Rawat]

On 7/10/2025 2:54 AM, Konrad Dybcio wrote:
> On 7/9/25 11:13 PM, Nitin Rawat wrote:
>>
>>
>> On 7/9/2025 10:46 AM, Avri Altman wrote:
>>>> Enable internal clock gating for QUnipro by setting the following attributes to 1
>>>> during host controller initialization:
>>>> - DL_VS_CLK_CFG
>>>> - PA_VS_CLK_CFG_REG
>>>> - DME_VS_CORE_CLK_CTRL.DME_HW_CGC_EN
>>>>
>>>> This change is necessary to support the internal clock gating mechanism in
>>>> Qualcomm UFS host controller. This is power saving feature and hence driver
>>>> can continue to function correctly despite any error in enabling these feature.
>>> Does this change offloads clock gating?
>>> i.e. no need to set UFSHCD_CAP_CLK_GATING ?
>> No , this change does not offload sw based UFS clock gating. Host controller has its own internal clock gating mechanism
> 
> Does QUnipro == "the UFS controller found on Qualcomm platforms"?
yes its same. I'll update the commit text of next patch set.
It's applicable for all Qualcomm UFS Controller version.

> 
> If so, please use some version of the latter name to make it more
> easily discernible
> 
> Konrad