From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D6092046A9 for ; Wed, 23 Jul 2025 16:59:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753289954; cv=none; b=kjJvEnCPTDJf1h21LZSJ5MuBJxyA4MmiAt8Y24KCXxnewk2/QwJI9Ips5lwRf+GbLesK6Zmb5v0ONa2ruhOw3JhnAuwziZ/oIjPuw6H6z13V5hS9Km5eM3vFLX7ZhKqBYwwmouCslAEkFhUgrqDV2k+UYbnC4Ot760AQfHZwgMA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753289954; c=relaxed/simple; bh=coFDtzQ8pIhFPG099ILzVcskcEfNooMBSxDKwyfGskE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uFg4bFBK2aNYTFoCVT/+TwkC9sj5q0OR2W+eVuvGoppRo46yTUFsWenNpblkkXsr8azkwaEfHsS9eQ5Q3gVh33Q0lRmTp+39Vg59i+rqj8AnKMq+rWruOGybySfSzDFRyHgJsdiFXoW/SDVUTdVl2QUX49lThUdpJtj2T8nz4+U= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=WEsHOwqu; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="WEsHOwqu" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1753289952; x=1784825952; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=coFDtzQ8pIhFPG099ILzVcskcEfNooMBSxDKwyfGskE=; b=WEsHOwquqx1IOWM8KWnXgQX9QlkeH4eXkttF+c7vKW2h9Ftb3cemZwdK 9DLqt7l+PJSTK3NPyINIOEwb6+eUSnAU1hXMWMcWnm7odADtgDIiMEkRo YlDmxbsxF0bRicwHDuZIdiO1FNX1x4aCu3BfhfGVbIgpGyYiRYMkWU1nK nHQWiz+Vwmazvq4bzZA6x0BhUTcbx39NvOGJm+YNEGOpQ+TyTtRq0qsgD lsl/Ethgsnu8pXGvpjZylP2rbneu50w/BBV3wN9zXevRhAxJkCk8PvRAP m6h8ipp4q3p7Rn3/uFB4EOPPfmON8lSf9BRo1PYlDW64ZsYh1RtR68+Rw g==; X-CSE-ConnectionGUID: SXyJEwHrSG2c1ITZ8FkRJA== X-CSE-MsgGUID: PwdWQJy3SV6mVwfx/ednkQ== X-IronPort-AV: E=McAfee;i="6800,10657,11501"; a="55734983" X-IronPort-AV: E=Sophos;i="6.16,333,1744095600"; d="scan'208";a="55734983" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jul 2025 09:59:12 -0700 X-CSE-ConnectionGUID: p7SI3lDMS/6zII9E+8P6QQ== X-CSE-MsgGUID: Azzv1uXNRGKBZp13L5NN+w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,333,1744095600"; d="scan'208";a="196732979" Received: from pgcooper-mobl3.ger.corp.intel.com (HELO localhost.localdomain) ([10.245.245.72]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jul 2025 09:59:10 -0700 From: Adrian Hunter To: Martin K Petersen Cc: James EJ Bottomley , Bart Van Assche , Avri Altman , Archana Patni , linux-scsi@vger.kernel.org Subject: [PATCH V2 1/8] scsi: ufs: ufs-pci: Fix hibernate state transition for Intel MTL-like host controllers Date: Wed, 23 Jul 2025 19:58:49 +0300 Message-ID: <20250723165856.145750-2-adrian.hunter@intel.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250723165856.145750-1-adrian.hunter@intel.com> References: <20250723165856.145750-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: 8bit From: Archana Patni UFSHCD core disables the UIC completion interrupt when issuing UIC hibernation commands, and re-enables it afterwards if it was enabled to start with, refer ufshcd_uic_pwr_ctrl(). For Intel MTL-like host controllers, accessing the register to re-enable the interrupt disrupts the state transition. Use hibern8_notify variant operation to disable the interrupt during the entire hibernation, thereby preventing the disruption. Fixes: 4049f7acef3eb ("scsi: ufs: ufs-pci: Add support for Intel MTL") Cc: stable@vger.kernel.org Signed-off-by: Archana Patni --- drivers/ufs/host/ufshcd-pci.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/ufs/host/ufshcd-pci.c b/drivers/ufs/host/ufshcd-pci.c index 996387906aa1..af1c272eef1c 100644 --- a/drivers/ufs/host/ufshcd-pci.c +++ b/drivers/ufs/host/ufshcd-pci.c @@ -216,6 +216,32 @@ static int ufs_intel_lkf_apply_dev_quirks(struct ufs_hba *hba) return ret; } +static void ufs_intel_ctrl_uic_compl(struct ufs_hba *hba, bool enable) +{ + u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); + + if (enable) + set |= UIC_COMMAND_COMPL; + else + set &= ~UIC_COMMAND_COMPL; + ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); +} + +static void ufs_intel_mtl_h8_notify(struct ufs_hba *hba, + enum uic_cmd_dme cmd, + enum ufs_notify_change_status status) +{ + /* + * Disable UIC COMPL INTR to prevent access to UFSHCI after + * checking HCS.UPMCRS + */ + if (status == PRE_CHANGE && cmd == UIC_CMD_DME_HIBER_ENTER) + ufs_intel_ctrl_uic_compl(hba, false); + + if (status == POST_CHANGE && cmd == UIC_CMD_DME_HIBER_EXIT) + ufs_intel_ctrl_uic_compl(hba, true); +} + #define INTEL_ACTIVELTR 0x804 #define INTEL_IDLELTR 0x808 @@ -533,6 +559,7 @@ static struct ufs_hba_variant_ops ufs_intel_mtl_hba_vops = { .init = ufs_intel_mtl_init, .exit = ufs_intel_common_exit, .hce_enable_notify = ufs_intel_hce_enable_notify, + .hibern8_notify = ufs_intel_mtl_h8_notify, .link_startup_notify = ufs_intel_link_startup_notify, .resume = ufs_intel_resume, .device_reset = ufs_intel_device_reset, -- 2.48.1