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Thu, 31 Jul 2025 00:16:02 -0700 (PDT) From: Krzysztof Kozlowski Date: Thu, 31 Jul 2025 09:15:52 +0200 Subject: [PATCH v2 1/3] dt-bindings: ufs: qcom: Split common part to qcom,ufs-common.yaml Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250731-dt-bindings-ufs-qcom-v2-1-53bb634bf95a@linaro.org> References: <20250731-dt-bindings-ufs-qcom-v2-0-53bb634bf95a@linaro.org> In-Reply-To: <20250731-dt-bindings-ufs-qcom-v2-0-53bb634bf95a@linaro.org> To: Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Bjorn Andersson , Andy Gross Cc: linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ram Kumar Dwivedi , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3812; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=FdLKYyZbfYSsvJ/xHFdBnLCPtWsxGyr4mVu3tlfgIuY=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBoixgtpbyamzGeGV64j4PYAWySsRXcPHf4pTMNi cys4OI/tmuJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaIsYLQAKCRDBN2bmhouD 102CD/0epYpzEUYS/+1bNoJeHulic14CNh2qachhO8i2BNMgc5gre4s0MvjTQ/ANjN+Job2FpK8 2sOtmlHu77GDoYOjtTkwEhggduI4A/RWFn4mvKtJtL2bffTsz9XL8xrd2lRLfIJQjQ7u+wkLRq2 6dQO6mhkN/tSW2HrFSOMaD1gm7hSmUK9qRurATvAp/Owa2PeTvWnzlxl+w5FcKJD2aKJ8za9QOf UZVdYAFBGclnZg/XjVRWe45cGS7V35aLS04MHiDzwADukzAxPZa30Rs7eZhGWZmh0qCki8/hzOT E+sH43NgmNR0rg5lHz/SxpEZA6CRIe8fd9xoLiYOABCraCj+xYQk9yG4zLo8iRmX+a2ReHBE1uS JOL/mY/1gCbb9TYOWUo8DGOawOMiZ3bQmWbhjfWQ2XtqHCpnyMtk1aKREysPCZJbgMma9OatU50 ZX+Zr57vSNIc/NKCHCqJjzgGSqXROP8v/AWcmKGfTI5FIMw9ThluqLCu7+Lyr+sw97DObOzokcp aNhZ5152zhg0Riep1mAkRm02ycGr5yw/xO0gP/SiF8D4SxgjJjLQXW8ad7QfYW6nzCE+53UDXjh EozzxUmPEe/qNHzYGIKnHKRjNnSvNu2OsXVdkFpE4mBdGvZLozetI8/5syKzgXcGyVg28Cu8GVw B2uz7y9OQCmWhDw== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B The binding for Qualcomm SoC UFS controllers grew and it will grow further. It already includes several conditionals, partially for difference in handling encryption block (ICE, either as phandle or as IO address space) but it will further grow for MCQ. Prepare for splitting this one big binding into several ones for common group of devices by defining common part for all Qualcomm UFS schemas. This only moves code, no functional impact expected. Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/ufs/qcom,ufs-common.yaml | 67 ++++++++++++++++++++++ .../devicetree/bindings/ufs/qcom,ufs.yaml | 53 +---------------- 2 files changed, 68 insertions(+), 52 deletions(-) diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs-common.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs-common.yaml new file mode 100644 index 0000000000000000000000000000000000000000..962dffcd28b44b3489be5615c75e7270a0c45dc4 --- /dev/null +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs-common.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ufs/qcom,ufs-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Universal Flash Storage (UFS) Controller Common Properties + +maintainers: + - Bjorn Andersson + +properties: + clocks: + minItems: 7 + maxItems: 9 + + clock-names: + minItems: 7 + maxItems: 9 + + dma-coherent: true + + interconnects: + minItems: 2 + maxItems: 2 + + interconnect-names: + items: + - const: ufs-ddr + - const: cpu-ufs + + iommus: + minItems: 1 + maxItems: 2 + + phys: + maxItems: 1 + + phy-names: + items: + - const: ufsphy + + power-domains: + maxItems: 1 + + required-opps: + maxItems: 1 + + resets: + maxItems: 1 + + '#reset-cells': + const: 1 + + reset-names: + items: + - const: rst + + reset-gpios: + maxItems: 1 + description: + GPIO connected to the RESET pin of the UFS memory device. + +allOf: + - $ref: ufs-common.yaml + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml index 6c6043d9809e1d6bf489153ab0aea5186d3563cc..fc0f7b8d1cd1c4a2168f29cffcc0c2ff660424df 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -47,39 +47,6 @@ properties: - const: qcom,ufshc - const: jedec,ufs-2.0 - clocks: - minItems: 7 - maxItems: 9 - - clock-names: - minItems: 7 - maxItems: 9 - - dma-coherent: true - - interconnects: - minItems: 2 - maxItems: 2 - - interconnect-names: - items: - - const: ufs-ddr - - const: cpu-ufs - - iommus: - minItems: 1 - maxItems: 2 - - phys: - maxItems: 1 - - phy-names: - items: - - const: ufsphy - - power-domains: - maxItems: 1 - qcom,ice: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to the Inline Crypto Engine node @@ -93,30 +60,12 @@ properties: - const: std - const: ice - required-opps: - maxItems: 1 - - resets: - maxItems: 1 - - '#reset-cells': - const: 1 - - reset-names: - items: - - const: rst - - reset-gpios: - maxItems: 1 - description: - GPIO connected to the RESET pin of the UFS memory device. - required: - compatible - reg allOf: - - $ref: ufs-common.yaml + - $ref: qcom,ufs-common.yaml - if: properties: -- 2.48.1