From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 841102D94AC for ; Wed, 24 Sep 2025 09:45:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758707146; cv=none; b=HX9yKSpJcIdMtCTDeRdYwtziSG0TjtGNFQHaHdvKUui1j0vmem5WqGAXqx7/eFbP30gFM74BUn4QHeQdCg9I0xIC6gt0S3JwOnIKKJ7F50gXaeMzHn55jd7wI6AzFyHoc2miNa9HRthZIErm7qOiYl40wj7IeELx0WRhiVdtccA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758707146; c=relaxed/simple; bh=cIpw4COKpQz08mLkJdFKiiwWn1X5G80IMv18BguV0zQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Ob2iVJATMGkHatoijDOcjdzlTJKUVwgWQ5QjtUXuOLvxovKlCC4/tyybWymGFONxvQxDQaqB1UaHb8nPsoGkgHEc3X1hrJ8AILkJ9zEJlOO84p2wSWtHjs/hD8eFhu606EHlITrqxNc9xlSXaFwdJRalFOCKxlksph3dh3R1USk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=iYrBPeQ5; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="iYrBPeQ5" X-UUID: 351ff806992b11f0b33aeb1e7f16c2b6-20250924 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=sqGBklntLZKIMD8bAyiyCe4dLV0cs5q4jSo499oZLmA=; b=iYrBPeQ5rVZl3zzIDPGFJAQi0mdEW8VBOfR/ZJhX61hr+3T1vxLjR/m8AmD20/7Eu6cEIEDNjxjpCd6HZ2C3wPQKUU48jfzFu31gjOYET4hANQ4XpGTzac3sK3qcyOhI+yW6Rkar28hcVmAbJJmluDuL23whao6MSheJblpB8VI=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.4,REQID:15770ae7-f0b7-4706-8ade-7d397f637c32,IP:0,UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:1ca6b93,CLOUDID:ef3be56c-8443-424b-b119-dc42e68239b0,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:-3,IP:nil,URL:0,File:130,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0, OSI:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 3,DMD|SSN|SDN X-CID-BAS: 3,DMD|SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 351ff806992b11f0b33aeb1e7f16c2b6-20250924 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 994584453; Wed, 24 Sep 2025 17:45:30 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 24 Sep 2025 17:45:28 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 24 Sep 2025 17:45:28 +0800 From: To: , CC: , , , , , , , , , , , , , , , Subject: [PATCH v2 3/8] ufs: host: mediatek: Handle clock scaling for high gear in PM flow Date: Wed, 24 Sep 2025 17:43:25 +0800 Message-ID: <20250924094527.2992256-4-peter.wang@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250924094527.2992256-1-peter.wang@mediatek.com> References: <20250924094527.2992256-1-peter.wang@mediatek.com> Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-MTK: N From: Peter Wang Add clock scaling down for power management flow in the UFS Mediatek driver. If clock scaling is disabled and fixed in high gear, ensure the clock scales down during suspend and scales up again after resume to support high gear. This adjustment maintains proper power management. Signed-off-by: Peter Wang --- drivers/ufs/host/ufs-mediatek.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c index 0622b7b32e51..1dcc0c7c9f9b 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -1778,6 +1778,9 @@ static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, if (ufshcd_is_clkscaling_supported(hba) && (host->clk_scale_up)) { ufshcd_pm_qos_update(hba, false); _ufs_mtk_clk_scale(hba, false); + } else if ((!ufshcd_is_clkscaling_supported(hba) && + hba->pwr_info.gear_rx >= UFS_HS_G5)) { + _ufs_mtk_clk_scale(hba, false); } return 0; @@ -1810,6 +1813,9 @@ static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) if (ufshcd_is_clkscaling_supported(hba) && (host->clk_scale_up)) { ufshcd_pm_qos_update(hba, true); _ufs_mtk_clk_scale(hba, true); + } else if ((!ufshcd_is_clkscaling_supported(hba) && + hba->pwr_info.gear_rx >= UFS_HS_G5)) { + _ufs_mtk_clk_scale(hba, true); } if (ufshcd_is_link_hibern8(hba)) { -- 2.45.2