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Bottomley" , linux-arm-msm@vger.kernel.org (open list:ARM/QUALCOMM MAILING LIST), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 10/11] scsi: ufs: ufs-qcom: Implement vops apply_tx_eqtr_settings() Date: Fri, 27 Feb 2026 08:08:07 -0800 Message-Id: <20260227160809.2620598-11-can.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260227160809.2620598-1-can.guo@oss.qualcomm.com> References: <20260227160809.2620598-1-can.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=WZwBqkhX c=1 sm=1 tr=0 ts=69a1c1b3 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=HzLeVaNsDn8A:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=W_4UrmeIGeJD-bvouaAA:9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjI3MDE0NCBTYWx0ZWRfXyQg35jh5XZgN HLUJWrHWYpdxKBjsX36ePHg+B/HjuNmPBLOLZlQEVujprwSMx8gHueaymB9CpSc++qtqkR4PsVD PrCc6oojVAB1UdU2O+vVMTuF6K4MvDsOI08WGo1Sn/Bf5XiS5yDTfoicXRb6fwrVmcDYFj7ej2t HiSZlCYieua8Uoh+qJKYDmSWOo+XQGP6RrRIWbbxLkuwO4yMwAUujJ3F8NbqTsyOkjoTcTqPRnX AEHcDLQWFB1SusH64sMNy1uGN27SO0D+eHtPUShMnTfqvviyRSthSyvg5qPurONJrMwla+iplAS 9W4L1bPNQoQShTKgpGnF0uPCYjldSYHMpupwEW7ukk3YucW3wXuVaeY3xijxGR2TT7ELudjBbYC Huokl9yf10nx9RC/B1NQfwfgIB7xl/1kXFFJTI0kVB/mlzsuEgc0sQTSpMayjmtMQALfouwIFA3 K8dJbQAuAE2FGTekXWQ== X-Proofpoint-ORIG-GUID: lttaQ2tkBb3bdv2dpmCtrMz88-w4F9va X-Proofpoint-GUID: lttaQ2tkBb3bdv2dpmCtrMz88-w4F9va X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-27_03,2026-02-27_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 bulkscore=0 clxscore=1011 malwarescore=0 adultscore=0 impostorscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602270144 On some platforms, when Host Software triggers TX Equalization Training, HW does not take TX EQTR settings programmed in PA_TxEQTRSetting, instead HW takes TX EQTR settings from PA_TxEQG1Setting. Implement vops apply_tx_eqtr_setting() to work around it by programming TX EQTR settings to PA_TxEQG1Setting during TX EQTR procedure. Signed-off-by: Can Guo --- drivers/ufs/host/ufs-qcom.c | 33 +++++++++++++++++++++++++++++++++ drivers/ufs/host/ufs-qcom.h | 2 ++ 2 files changed, 35 insertions(+) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 7115d87882b1..8582396fa0d8 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -2842,6 +2842,28 @@ static int ufs_qcom_get_rx_fom(struct ufs_hba *hba, return ret; } +static int ufs_qcom_apply_tx_eqtr_settings(struct ufs_hba *hba, + struct ufs_pa_layer_attr *pwr_mode, + struct tx_eqtr_iter *h_iter, + struct tx_eqtr_iter *d_iter) +{ + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + u32 setting = 0; + int lane, ret; + + if (host->hw_ver.major != 0x7 || host->hw_ver.minor > 0x1) + return 0; + + for (lane = 0; lane < h_iter->num_lanes; lane++) { + setting |= TX_HS_PRESHOOT_BITS(lane, h_iter->preshoot); + setting |= TX_HS_DEEMPHASIS_BITS(lane, h_iter->deemphasis); + } + + ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXEQG1SETTING), setting); + + return ret; +} + static int ufs_qcom_tx_eqtr_notify(struct ufs_hba *hba, enum ufs_notify_change_status status, struct ufshcd_tx_eq_params *params, @@ -2865,6 +2887,11 @@ static int ufs_qcom_tx_eqtr_notify(struct ufs_hba *hba, return 0; if (status == PRE_CHANGE) { + ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TXEQG1SETTING), + &host->saved_tx_eq_g1_setting); + if (ret) + return ret; + /* PMC to target HS Gear. */ ret = ufs_qcom_change_power_mode(hba, pwr_mode, /*force_pmc=*/false); @@ -2872,6 +2899,11 @@ static int ufs_qcom_tx_eqtr_notify(struct ufs_hba *hba, dev_err(hba->dev, "%s: Failed to change power mode to target HS-G%u, Rate-%s: %d\n", __func__, gear, UFS_HS_RATE_STRING(rate), ret); } else { + ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXEQG1SETTING), + host->saved_tx_eq_g1_setting); + if (ret) + return ret; + /* PMC back to HS-G1. */ ret = ufs_qcom_change_power_mode(hba, &pwr_mode_hs_g1, /*force_pmc=*/false); @@ -2914,6 +2946,7 @@ static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = { .config_esi = ufs_qcom_config_esi, .freq_to_gear_speed = ufs_qcom_freq_to_gear_speed, .get_rx_fom = ufs_qcom_get_rx_fom, + .apply_tx_eqtr_settings = ufs_qcom_apply_tx_eqtr_settings, .tx_eqtr_notify = ufs_qcom_tx_eqtr_notify, }; diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 66fb42453e5c..ebe4e07c7da1 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -350,6 +350,8 @@ struct ufs_qcom_host { u32 phy_gear; bool esi_enabled; + + u32 saved_tx_eq_g1_setting; }; struct ufs_qcom_drvdata { -- 2.34.1