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J . Bottomley" , "Martin K . Petersen" , Pedro Sousa , Arnd Bergmann , AngeloGioacchino Del Regno , Conor Dooley , Rob Herring , Krzysztof Kozlowski , linux-scsi@vger.kernel.org Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Minda Chen Subject: [PATCH v2 2/3] scsi: ufs: dwc: Rename amd-versal2 read/write PHY API and move to dwc common file Date: Sat, 9 May 2026 14:27:58 +0800 Message-Id: <20260509062759.125472-3-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260509062759.125472-1-minda.chen@starfivetech.com> References: <20260509062759.125472-1-minda.chen@starfivetech.com> Content-Type: text/plain X-ClientProxiedBy: ZQ0PR01CA0018.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:5::15) To BJXPR01MB0855.CHNPR01.prod.partner.outlook.cn (2406:e500:c211:18::12) Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BJXPR01MB0855:EE_|BJXPR01MB0632:EE_ X-MS-Office365-Filtering-Correlation-Id: 4c2e7665-7f14-4942-9b7b-08dead9423b8 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|7416014|52116014|1800799024|56012099003|22082099003|18002099003|38350700014|921020|3023799003; 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The read/write PHY register API are common functions for designware ufs PHY. For other vendors reuse the code, move to common ufshcd-dwc.c file. Signed-off-by: Minda Chen --- drivers/ufs/host/ufs-amd-versal2.c | 85 ++++++------------------------ drivers/ufs/host/ufshcd-dwc.c | 53 +++++++++++++++++++ drivers/ufs/host/ufshcd-dwc.h | 2 + 3 files changed, 72 insertions(+), 68 deletions(-) diff --git a/drivers/ufs/host/ufs-amd-versal2.c b/drivers/ufs/host/ufs-amd-versal2.c index 2154d6286817..2e671881e7ae 100644 --- a/drivers/ufs/host/ufs-amd-versal2.c +++ b/drivers/ufs/host/ufs-amd-versal2.c @@ -43,57 +43,6 @@ struct ufs_versal2_host { u8 ctlecompval1; }; -static int ufs_versal2_phy_reg_write(struct ufs_hba *hba, u32 addr, u32 val) -{ - static struct ufshcd_dme_attr_val phy_write_attrs[] = { - { UIC_ARG_MIB(CBCREGADDRLSB), 0, DME_LOCAL }, - { UIC_ARG_MIB(CBCREGADDRMSB), 0, DME_LOCAL }, - { UIC_ARG_MIB(CBCREGWRLSB), 0, DME_LOCAL }, - { UIC_ARG_MIB(CBCREGWRMSB), 0, DME_LOCAL }, - { UIC_ARG_MIB(CBCREGRDWRSEL), 1, DME_LOCAL }, - { UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL } - }; - - phy_write_attrs[0].mib_val = (u8)addr; - phy_write_attrs[1].mib_val = (u8)(addr >> 8); - phy_write_attrs[2].mib_val = (u8)val; - phy_write_attrs[3].mib_val = (u8)(val >> 8); - - return ufshcd_dwc_dme_set_attrs(hba, phy_write_attrs, ARRAY_SIZE(phy_write_attrs)); -} - -static int ufs_versal2_phy_reg_read(struct ufs_hba *hba, u32 addr, u32 *val) -{ - u32 mib_val; - int ret; - static struct ufshcd_dme_attr_val phy_read_attrs[] = { - { UIC_ARG_MIB(CBCREGADDRLSB), 0, DME_LOCAL }, - { UIC_ARG_MIB(CBCREGADDRMSB), 0, DME_LOCAL }, - { UIC_ARG_MIB(CBCREGRDWRSEL), 0, DME_LOCAL }, - { UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL } - }; - - phy_read_attrs[0].mib_val = (u8)addr; - phy_read_attrs[1].mib_val = (u8)(addr >> 8); - - ret = ufshcd_dwc_dme_set_attrs(hba, phy_read_attrs, ARRAY_SIZE(phy_read_attrs)); - if (ret) - return ret; - - ret = ufshcd_dme_get(hba, UIC_ARG_MIB(CBCREGRDLSB), &mib_val); - if (ret) - return ret; - - *val = mib_val; - ret = ufshcd_dme_get(hba, UIC_ARG_MIB(CBCREGRDMSB), &mib_val); - if (ret) - return ret; - - *val |= (mib_val << 8); - - return 0; -} - static int ufs_versal2_enable_phy(struct ufs_hba *hba) { u32 offset, reg; @@ -162,64 +111,64 @@ static int ufs_versal2_setup_phy(struct ufs_hba *hba) u32 reg; /* Bypass RX-AFE offset calibrations (ATT/CTLE) */ - ret = ufs_versal2_phy_reg_read(hba, FAST_FLAGS(0), ®); + ret = ufs_dwc_phy_reg_read(hba, FAST_FLAGS(0), ®); if (ret) return ret; reg |= MPHY_FAST_RX_AFE_CAL; - ret = ufs_versal2_phy_reg_write(hba, FAST_FLAGS(0), reg); + ret = ufs_dwc_phy_reg_write(hba, FAST_FLAGS(0), reg); if (ret) return ret; - ret = ufs_versal2_phy_reg_read(hba, FAST_FLAGS(1), ®); + ret = ufs_dwc_phy_reg_read(hba, FAST_FLAGS(1), ®); if (ret) return ret; reg |= MPHY_FAST_RX_AFE_CAL; - ret = ufs_versal2_phy_reg_write(hba, FAST_FLAGS(1), reg); + ret = ufs_dwc_phy_reg_write(hba, FAST_FLAGS(1), reg); if (ret) return ret; /* Program ATT and CTLE compensation values */ if (host->attcompval0) { - ret = ufs_versal2_phy_reg_write(hba, RX_AFE_ATT_IDAC(0), host->attcompval0); + ret = ufs_dwc_phy_reg_write(hba, RX_AFE_ATT_IDAC(0), host->attcompval0); if (ret) return ret; } if (host->attcompval1) { - ret = ufs_versal2_phy_reg_write(hba, RX_AFE_ATT_IDAC(1), host->attcompval1); + ret = ufs_dwc_phy_reg_write(hba, RX_AFE_ATT_IDAC(1), host->attcompval1); if (ret) return ret; } if (host->ctlecompval0) { - ret = ufs_versal2_phy_reg_write(hba, RX_AFE_CTLE_IDAC(0), host->ctlecompval0); + ret = ufs_dwc_phy_reg_write(hba, RX_AFE_CTLE_IDAC(0), host->ctlecompval0); if (ret) return ret; } if (host->ctlecompval1) { - ret = ufs_versal2_phy_reg_write(hba, RX_AFE_CTLE_IDAC(1), host->ctlecompval1); + ret = ufs_dwc_phy_reg_write(hba, RX_AFE_CTLE_IDAC(1), host->ctlecompval1); if (ret) return ret; } - ret = ufs_versal2_phy_reg_read(hba, FW_CALIB_CCFG(0), ®); + ret = ufs_dwc_phy_reg_read(hba, FW_CALIB_CCFG(0), ®); if (ret) return ret; reg |= MPHY_FW_CALIB_CFG_VAL; - ret = ufs_versal2_phy_reg_write(hba, FW_CALIB_CCFG(0), reg); + ret = ufs_dwc_phy_reg_write(hba, FW_CALIB_CCFG(0), reg); if (ret) return ret; - ret = ufs_versal2_phy_reg_read(hba, FW_CALIB_CCFG(1), ®); + ret = ufs_dwc_phy_reg_read(hba, FW_CALIB_CCFG(1), ®); if (ret) return ret; reg |= MPHY_FW_CALIB_CFG_VAL; - return ufs_versal2_phy_reg_write(hba, FW_CALIB_CCFG(1), reg); + return ufs_dwc_phy_reg_write(hba, FW_CALIB_CCFG(1), reg); } static int ufs_versal2_phy_init(struct ufs_hba *hba) @@ -406,7 +355,7 @@ static int ufs_versal2_phy_ratesel(struct ufs_hba *hba, u32 activelanes, u32 rx_ for (lane = 0; lane < activelanes; lane++) { time_left = TIMEOUT_MICROSEC; - ret = ufs_versal2_phy_reg_read(hba, RX_OVRD_IN_1(lane), ®); + ret = ufs_dwc_phy_reg_read(hba, RX_OVRD_IN_1(lane), ®); if (ret) return ret; @@ -416,12 +365,12 @@ static int ufs_versal2_phy_ratesel(struct ufs_hba *hba, u32 activelanes, u32 rx_ else reg &= ~MPHY_RX_OVRD_VAL; - ret = ufs_versal2_phy_reg_write(hba, RX_OVRD_IN_1(lane), reg); + ret = ufs_dwc_phy_reg_write(hba, RX_OVRD_IN_1(lane), reg); if (ret) return ret; do { - ret = ufs_versal2_phy_reg_read(hba, RX_PCS_OUT(lane), ®); + ret = ufs_dwc_phy_reg_read(hba, RX_PCS_OUT(lane), ®); if (ret) return ret; @@ -483,12 +432,12 @@ static int ufs_versal2_pwr_change_notify(struct ufs_hba *hba, enum ufs_notify_ch /* Remove rx_req override */ for (lane = 0; lane < dev_req_params->lane_tx; lane++) { - ret = ufs_versal2_phy_reg_read(hba, RX_OVRD_IN_1(lane), ®); + ret = ufs_dwc_phy_reg_read(hba, RX_OVRD_IN_1(lane), ®); if (ret) return ret; reg &= ~MPHY_RX_OVRD_EN; - ret = ufs_versal2_phy_reg_write(hba, RX_OVRD_IN_1(lane), reg); + ret = ufs_dwc_phy_reg_write(hba, RX_OVRD_IN_1(lane), reg); if (ret) return ret; } diff --git a/drivers/ufs/host/ufshcd-dwc.c b/drivers/ufs/host/ufshcd-dwc.c index 21b1cf912dcc..b057a78e151c 100644 --- a/drivers/ufs/host/ufshcd-dwc.c +++ b/drivers/ufs/host/ufshcd-dwc.c @@ -15,6 +15,59 @@ #include "ufshcd-dwc.h" #include "ufshci-dwc.h" +int ufs_dwc_phy_reg_write(struct ufs_hba *hba, u32 addr, u32 val) +{ + static struct ufshcd_dme_attr_val phy_write_attrs[] = { + { UIC_ARG_MIB(CBCREGADDRLSB), 0, DME_LOCAL }, + { UIC_ARG_MIB(CBCREGADDRMSB), 0, DME_LOCAL }, + { UIC_ARG_MIB(CBCREGWRLSB), 0, DME_LOCAL }, + { UIC_ARG_MIB(CBCREGWRMSB), 0, DME_LOCAL }, + { UIC_ARG_MIB(CBCREGRDWRSEL), 1, DME_LOCAL }, + { UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL } + }; + + phy_write_attrs[0].mib_val = (u8)addr; + phy_write_attrs[1].mib_val = (u8)(addr >> 8); + phy_write_attrs[2].mib_val = (u8)val; + phy_write_attrs[3].mib_val = (u8)(val >> 8); + + return ufshcd_dwc_dme_set_attrs(hba, phy_write_attrs, ARRAY_SIZE(phy_write_attrs)); +} +EXPORT_SYMBOL(ufs_dwc_phy_reg_write); + +int ufs_dwc_phy_reg_read(struct ufs_hba *hba, u32 addr, u32 *val) +{ + u32 mib_val; + int ret; + static struct ufshcd_dme_attr_val phy_read_attrs[] = { + { UIC_ARG_MIB(CBCREGADDRLSB), 0, DME_LOCAL }, + { UIC_ARG_MIB(CBCREGADDRMSB), 0, DME_LOCAL }, + { UIC_ARG_MIB(CBCREGRDWRSEL), 0, DME_LOCAL }, + { UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL } + }; + + phy_read_attrs[0].mib_val = (u8)addr; + phy_read_attrs[1].mib_val = (u8)(addr >> 8); + + ret = ufshcd_dwc_dme_set_attrs(hba, phy_read_attrs, ARRAY_SIZE(phy_read_attrs)); + if (ret) + return ret; + + ret = ufshcd_dme_get(hba, UIC_ARG_MIB(CBCREGRDLSB), &mib_val); + if (ret) + return ret; + + *val = mib_val; + ret = ufshcd_dme_get(hba, UIC_ARG_MIB(CBCREGRDMSB), &mib_val); + if (ret) + return ret; + + *val |= (mib_val << 8); + + return 0; +} +EXPORT_SYMBOL(ufs_dwc_phy_reg_read); + int ufshcd_dwc_dme_set_attrs(struct ufs_hba *hba, const struct ufshcd_dme_attr_val *v, int n) { diff --git a/drivers/ufs/host/ufshcd-dwc.h b/drivers/ufs/host/ufshcd-dwc.h index c618bb914904..8091f186a9b3 100644 --- a/drivers/ufs/host/ufshcd-dwc.h +++ b/drivers/ufs/host/ufshcd-dwc.h @@ -68,4 +68,6 @@ int ufshcd_dwc_link_startup_notify(struct ufs_hba *hba, enum ufs_notify_change_status status); int ufshcd_dwc_dme_set_attrs(struct ufs_hba *hba, const struct ufshcd_dme_attr_val *v, int n); +int ufs_dwc_phy_reg_write(struct ufs_hba *hba, u32 addr, u32 val); +int ufs_dwc_phy_reg_read(struct ufs_hba *hba, u32 addr, u32 *val); #endif /* End of Header */ -- 2.17.1