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[144.49.247.11]) by smtp-relay.gmail.com with ESMTPS id 5a478bee46e88-31174a0ae6csm351476eec.18.2026.07.08.11.40.37 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 08 Jul 2026 11:40:37 -0700 (PDT) X-Relaying-Domain: broadcom.com X-CFilter-Loop: Reflected Received: by mail-pg1-f200.google.com with SMTP id 41be03b00d2f7-c88fc985a65so1471227a12.2 for ; Wed, 08 Jul 2026 11:40:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1783536036; x=1784140836; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=uG/LgOddo79527I5ewTqybf625TfZNLE1GUR11MXTKk=; b=KBcASSFE6AYQpeBru8cXTsPbNOLxBQxh97PNb4bO4JFY9ijwVKCuHbI5UF6V+6lQNr Kqjm12YNLmT5h8L+plFEpy4iYNvKbKbU8bfLD6q7ewCqlaqtuZbzEpFZpeNXxsVf/GEN RN/OaJsAWAc6ETewK4WlaH2BbwpGyPwKhKUdc= X-Received: by 2002:a05:6a21:62c6:b0:398:837a:7af0 with SMTP id adf61e73a8af0-3c0bd04207cmr4167765637.30.1783536035784; Wed, 08 Jul 2026 11:40:35 -0700 (PDT) X-Received: by 2002:a05:6a21:62c6:b0:398:837a:7af0 with SMTP id adf61e73a8af0-3c0bd04207cmr4167731637.30.1783536035200; Wed, 08 Jul 2026 11:40:35 -0700 (PDT) Received: from localhost.localdomain ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3117d847e17sm19820599eec.18.2026.07.08.11.40.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jul 2026 11:40:34 -0700 (PDT) From: Ranjan Kumar To: linux-scsi@vger.kernel.org, martin.petersen@oracle.com Cc: sathya.prakash@broadcom.com, chandrakanth.patil@broadcom.com, vishakhavc@google.com, ipylypiv@google.com, Ranjan Kumar , Sashiko Subject: [PATCH v2 04/10] mpi3mr: Fix NVMe page size caching for non-operational devices Date: Thu, 9 Jul 2026 00:02:59 +0530 Message-ID: <20260708183305.244485-5-ranjan.kumar@broadcom.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260708183305.244485-1-ranjan.kumar@broadcom.com> References: <20260708183305.244485-1-ranjan.kumar@broadcom.com> Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-DetectorID-Processed: b00c1d49-9d2e-4205-b15f-d015386d3d5e For NVMe devices reported with an error access status, the cached PCIe page size may remain unset during device discovery. This causes management IOCTL validation to fail, preventing requests from reaching firmware and resulting in an incorrect error being returned to user space. Populate the page size attribute irrespective of device access status so that management IOCTLs are processed by firmware and the appropriate device-specific error is reported. Additionally, add bounds checking for the firmware-provided page_size. If the device is in an error state, the firmware might return invalid data. Unvalidated values could lead to undefined behavior or kernel panics during later bitwise shift operations. Fall back to a default page size of 4096 bytes (shift exponent 12) if the value is invalid. Reported-by: Sashiko Closes: https://sashiko.dev/#/patchset/20260626114109.43685-1-ranjan.kumar@broadcom.com?part=4 Signed-off-by: Chandrakanth Patil Signed-off-by: Ranjan Kumar --- drivers/scsi/mpi3mr/mpi3mr_os.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/scsi/mpi3mr/mpi3mr_os.c b/drivers/scsi/mpi3mr/mpi3mr_os.c index d2a20f2721db..df7365d19b44 100644 --- a/drivers/scsi/mpi3mr/mpi3mr_os.c +++ b/drivers/scsi/mpi3mr/mpi3mr_os.c @@ -1354,12 +1354,14 @@ static void mpi3mr_update_tgtdev(struct mpi3mr_ioc *mrioc, tgtdev->dev_spec.pcie_inf.capb = le32_to_cpu(pcieinf->capabilities); tgtdev->dev_spec.pcie_inf.mdts = MPI3MR_DEFAULT_MDTS; - /* 2^12 = 4096 */ - tgtdev->dev_spec.pcie_inf.pgsz = 12; + /* Validate firmware page size to prevent undefined shift behavior */ + if (pcieinf->page_size > 0 && pcieinf->page_size < 31) + tgtdev->dev_spec.pcie_inf.pgsz = pcieinf->page_size; + else + tgtdev->dev_spec.pcie_inf.pgsz = 12; /* Default to 4096 (2^12) */ if (dev_pg0->access_status == MPI3_DEVICE0_ASTATUS_NO_ERRORS) { tgtdev->dev_spec.pcie_inf.mdts = le32_to_cpu(pcieinf->maximum_data_transfer_size); - tgtdev->dev_spec.pcie_inf.pgsz = pcieinf->page_size; tgtdev->dev_spec.pcie_inf.reset_to = max_t(u8, pcieinf->controller_reset_to, MPI3MR_INTADMCMD_TIMEOUT); -- 2.47.3