From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F3F945C6E5; Tue, 1 Sep 2026 15:39:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788277173; cv=none; b=IFTijzkME+oj2MjSOQHpjXSedSou1ibXRNgzfbW3702j6ozS68JOBreoZIz9zmDbKvU7hCyiuPkAgtghzraw+fKAIGlrK1Gms1W2viOEZh2I0AQSy1pt4iqNeyP5rQeZK7MVL6lqgZpDvn6OgDku4vKuYnAkAQmys7vS9NJyCcQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788277173; c=relaxed/simple; bh=bWpqNA2w/lzQwaLDZK22KciiLovKewpkb+MzEY+uZ6Y=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Hg8VYpwbptsLlWFWUFC/QhFlSiVKea/V2teHZra07qyemUWCEVBDdgJO8IvLfQd/NEABUwZjg85FPOIVBvduI575YTh9HMFT6axnqZwF8tDpLPMMk1NO8mMF6jgE1Xw6avFdZKCXvKv9veBUTUvSnBB9WbIt7CkHyAPGjebS0zw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=TyZVHtLo; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="TyZVHtLo" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1788277170; bh=bWpqNA2w/lzQwaLDZK22KciiLovKewpkb+MzEY+uZ6Y=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=TyZVHtLoQNfuEKgHq5EWoOaKXm6zuIymHKiF1a1mlPm11tpXRQMSK31C8IZrXiF78 rE+1iBfJEuQstjof1WlSIoETwvyoWfxuicfyA2FovsNjOzjfdRWdtKPblhllXT173n fD+MeqkvhUk4+hZCuTiLMI8ql42Qs4Hku8QBMvXaiAuZraJNlCvz+eAYyk6NHXr8WM nV4zypNfGfECP05lQBsVUOHKzec9oICIwUcxPn9rArS8TlgILoXWYlMDnZzyZcf/ad vFHHKYspQlwpTq8rCsyX5vWt3Pcs6lCiHrOIRK+ZHNimB4I3kRCSA2R3msHidArNiq RfyOIpOHOSj3w== Received: from yukiji.home (unknown [100.64.0.131]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laeyraud) by bali.collaboradmins.com (Postfix) with ESMTPSA id 9D6A217E0FD2; Tue, 01 Sep 2026 17:39:29 +0200 (CEST) From: Louis-Alexis Eyraud Date: Tue, 01 Sep 2026 17:38:53 +0200 Subject: [PATCH v11 05/24] phy: mediatek: ufs: Add support for resets Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260901-mt8196-ufs-v11-5-dbd007704490@collabora.com> References: <20260901-mt8196-ufs-v11-0-dbd007704490@collabora.com> In-Reply-To: <20260901-mt8196-ufs-v11-0-dbd007704490@collabora.com> To: Chunfeng Yun , Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Peter Wang , Chaotian Jing , Alim Akhtar , Avri Altman , Bart Van Assche , Stanley Jhu , "James E.J. Bottomley" , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , "Martin K. Petersen" , "Martin K. Petersen" Cc: kernel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nicolas Frattaroli , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788277163; l=4162; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=2rm7VAJlRoymYlJ4TRbEdX+nNHudWfCFJbmQirU4tfo=; b=JnRCnn4T/3OXf3PYU2+VDL65IBmglLKhkJdhCbwhD1tonaYeBmJvm376LGXA3+0kV41tSCqDc z0LPxWVXqEGBMXT3uTBCTi2b4ifIa0YrcVLxhugn31Lkaj123PAS0g2 X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= From: Nicolas Frattaroli The MediaTek UFS PHY supports PHY resets. Until now, they've been implemented in the UFS host driver. Since they were never documented in the UFS HCI node's DT bindings, and no mainline DT uses it, it's fine if it's moved to the correct location, which is the PHY driver. Implement the MPHY reset logic in this driver and expose it through the phy subsystem's reset op. The reset itself is optional, as judging by other mainline devices that use this hardware, it's not required for the device to function. If no reset is present, the reset op returns -EOPNOTSUPP, which means that the ufshci driver can detect it's present and not double sleep in its own reset function, where it will call the phy reset. Reviewed-by: Philipp Zabel Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Peter Wang Acked-by: Vinod Koul Signed-off-by: Nicolas Frattaroli Signed-off-by: Louis-Alexis Eyraud --- drivers/phy/mediatek/phy-mtk-ufs.c | 71 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/drivers/phy/mediatek/phy-mtk-ufs.c b/drivers/phy/mediatek/phy-mtk-ufs.c index fc19e0fa8ed5..4439a9eb6b7a 100644 --- a/drivers/phy/mediatek/phy-mtk-ufs.c +++ b/drivers/phy/mediatek/phy-mtk-ufs.c @@ -4,12 +4,15 @@ * Author: Stanley Chu */ +#include #include #include #include #include #include #include +#include +#include #include "phy-mtk-io.h" @@ -35,9 +38,17 @@ #define UFSPHY_CLKS_CNT 2 +#define UFS_MTK_SIP_MPHY_CTRL BIT(8) + +enum ufs_mtk_mphy_op { + UFS_MPHY_BACKUP = 0, + UFS_MPHY_RESTORE +}; + struct ufs_mtk_phy { struct device *dev; void __iomem *mmio; + struct reset_control *reset; struct clk_bulk_data clks[UFSPHY_CLKS_CNT]; }; @@ -140,9 +151,59 @@ static int ufs_mtk_phy_power_off(struct phy *generic_phy) return 0; } +static int ufs_mtk_phy_ctrl(struct ufs_mtk_phy *phy, enum ufs_mtk_mphy_op op) +{ + struct arm_smccc_res res; + + arm_smccc_smc(MTK_SIP_UFS_CONTROL, UFS_MTK_SIP_MPHY_CTRL, op, + 0, 0, 0, 0, 0, &res); + + switch (res.a0) { + case SMCCC_RET_NOT_SUPPORTED: + return -EOPNOTSUPP; + case SMCCC_RET_INVALID_PARAMETER: + return -EINVAL; + default: + return 0; + } +} + +static int ufs_mtk_phy_reset(struct phy *generic_phy) +{ + struct ufs_mtk_phy *phy = get_ufs_mtk_phy(generic_phy); + int ret; + + if (!phy->reset) + return -EOPNOTSUPP; + + ret = reset_control_assert(phy->reset); + if (ret) + return ret; + + usleep_range(100, 110); + + ret = reset_control_deassert(phy->reset); + if (ret) + return ret; + + /* + * To avoid double-sleep and other unintended side-effects in the ufshci + * driver, don't return the phy_ctrl retval here, but just return -EPROTO. + */ + ret = ufs_mtk_phy_ctrl(phy, UFS_MPHY_RESTORE); + if (ret) { + dev_err(phy->dev, "UFS_MPHY_RESTORE SMC command failed: %pe\n", + ERR_PTR(ret)); + return -EPROTO; + } + + return 0; +} + static const struct phy_ops ufs_mtk_phy_ops = { .power_on = ufs_mtk_phy_power_on, .power_off = ufs_mtk_phy_power_off, + .reset = ufs_mtk_phy_reset, .owner = THIS_MODULE, }; @@ -162,8 +223,18 @@ static int ufs_mtk_phy_probe(struct platform_device *pdev) if (IS_ERR(phy->mmio)) return PTR_ERR(phy->mmio); + phy->reset = devm_reset_control_get_optional_exclusive(dev, NULL); + if (IS_ERR(phy->reset)) + return dev_err_probe(dev, PTR_ERR(phy->reset), "Failed to get reset\n"); + phy->dev = dev; + if (phy->reset) { + ret = ufs_mtk_phy_ctrl(phy, UFS_MPHY_BACKUP); + if (ret) + return dev_err_probe(dev, ret, "Failed to back up MPHY\n"); + } + ret = ufs_mtk_phy_clk_init(phy); if (ret) return ret; -- 2.55.0