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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDA3MDA0MyBTYWx0ZWRfX0JFhZgNxAA/S jnXtbRTUxVHVlj8aPUZT+im+7QxRDYRAPdTI7xE+845ceab2/qb9tPNa6mXqe9MRAwXLrXTlgW2 yobnqiyozVgPysChtf7fGd77YR9HUPE= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDA3MDA0MyBTYWx0ZWRfX5wYMup8iVXjo NIy9zbjKcL4kRwfM7iPN0y1Q09JRkw0j4kshga5GVzcyxzQE9iCNYWxLZ0tmhwEmIdKdFpux+1N LJXiA128KB5oW8Db6bBzWCvki2HnGYed5okBVrCMlCU2uPXfReX5nwSJ4o7qalQBhjcFBEL2ZMs EpjSMHezVPBSLiXDfyCB3tJ3r92mk4jy2pZCaBmqfh3xyICzyo4wTl45vCG4PRzhiQmHqT1iLGn O4tx6+ySyhTa75EifYvUNo2vmxaBKtJF9NRr7camBMv/uY1grQOA+Rp9XchYdZTNGF+bSfE3bMs feYsyN+CsbSMx52IGMdnM/d+4cV6ixYByZGDOYz2tlSQn+a0OmH0iEUmMrAr8aCs8fJ1dqf8ENO DuThqOaNv5x7nBVEvN74an4Mntm5h0bQMP80vEuSNmS+MVT9hU1cKoZde7FcG9i7Vn4CIDjazas PDdGf7x0shx+Oj6EiUw== X-Proofpoint-GUID: L-4vJLkjHA_SFqVz--vXCxcoO4ONXzQW X-Proofpoint-ORIG-GUID: L-4vJLkjHA_SFqVz--vXCxcoO4ONXzQW X-Authority-Analysis: v=2.4 cv=LvYHWXdc c=1 sm=1 tr=0 ts=6ac62646 cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=SwwKY9vyf4oML-p5yksA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-07_03,2026-10-06_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 adultscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2610070043 On 10/7/2026 1:13 PM, Dmitry Baryshkov wrote: > On Wed, Oct 07, 2026 at 11:59:36AM +0530, Pradeep P V K wrote: >> Add UFS PHY and UFS host controller nodes for Glymur SoC. >> >> Reviewed-by: Abel Vesa >> Signed-off-by: Pradeep P V K >> --- >> arch/arm64/boot/dts/qcom/glymur.dtsi | 125 ++++++++++++++++++++++++++++++++++- >> 1 file changed, 122 insertions(+), 3 deletions(-) >> >> @@ -4102,6 +4102,125 @@ rng: rng@10c3000 { >> reg = <0x0 0x010c3000 0x0 0x1000>; >> }; >> >> + ufs_mem_phy: phy@1d80000 { >> + compatible = "qcom,glymur-qmp-ufs-phy"; >> + reg = <0x0 0x01d80000 0x0 0x2000>; >> + >> + clocks = <&rpmhcc RPMH_CXO_CLK>, >> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, >> + /* UFS and PCIE4 share the same clkref */ >> + <&tcsr TCSR_PCIE_4_CLKREF_EN>; >> + >> + clock-names = "ref", >> + "ref_aux", >> + "qref"; >> + >> + resets = <&ufs_mem_hc 0>; >> + reset-names = "ufsphy"; > > power-domains = <&gcc GCC_UFS_PHY_GDSC> ? Or is there > GCC_UFS_MEM_PHY_GDSC, which is simply not described in gcc? > > If there are none, it should be reflected in the DT bindings, together > with the explanation in the commit message. > Yes, Glymur SoC does not support UFS PHY GDSC. Sure, i will update the DT-bindings accordingly and include the explanation in the commit of next patch series. >> + >> + #clock-cells = <1>; >> + #phy-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >