[PATCH v2 03/15] scsi: ufs: ufs-exynos: change pclk available max value

Chanho Park
2021-07-14T07:12:11Z

To support 167MHz PCLK, we need to adjust the maximum value.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
---
drivers/scsi/ufs/ufs-exynos.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/scsi/ufs/ufs-exynos.h b/drivers/scsi/ufs/ufs-exynos.h
index 67505fe32ebf..475a5adf0f8b 100644
--- a/drivers/scsi/ufs/ufs-exynos.h
+++ b/drivers/scsi/ufs/ufs-exynos.h
@@ -99,7 +99,7 @@ struct exynos_ufs;
#define PA_HIBERN8TIME_VAL 0x20

#define PCLK_AVAIL_MIN 70000000
-#define PCLK_AVAIL_MAX 133000000
+#define PCLK_AVAIL_MAX 167000000

struct exynos_ufs_uic_attr {
/* TX Attributes */
--
2.32.0