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Petersen" CC: , "James E.J. Bottomley" , Peter Wang , Manivannan Sadhasivam , Avri Altman , "Andrew Halaney" , Bean Huo , Alim Akhtar , Eric Biggers , Minwoo Im , Maramaina Naresh References: <20240821182923.145631-1-bvanassche@acm.org> <20240821182923.145631-3-bvanassche@acm.org> <41e5ed21-8ea6-3a4c-2f25-922458593f38@quicinc.com> <6e8df17b-320e-4bfc-a0be-c7918b0263d4@acm.org> <6fceba57-e1f6-e76b-94f3-1684c1fe6e98@quicinc.com> <85481ed2-a911-41a4-8fd4-80e4d20dbf04@acm.org> From: "Bao D. Nguyen" In-Reply-To: <85481ed2-a911-41a4-8fd4-80e4d20dbf04@acm.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: XDti8fck53HBXN6Nt-p5zspzY9JU6Icf X-Proofpoint-GUID: XDti8fck53HBXN6Nt-p5zspzY9JU6Icf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-22_14,2024-08-22_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 mlxscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 impostorscore=0 clxscore=1015 spamscore=0 mlxlogscore=999 phishscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408220156 On 8/22/2024 11:13 AM, Bart Van Assche wrote: > On 8/21/24 6:05 PM, Bao D. Nguyen wrote: >> If I understand correctly, the link is hibernated because we had a >> successful ufshcd_uic_hibern8_enter() earlier. Then the >> ufshcd_uic_pwr_ctrl() is invoked probably from a power mode change >> command? (a callstack would be helpful in this case). > > Hi Bao, > > ufshcd_uic_hibern8_enter() calls ufshcd_uic_pwr_ctrl() directly. The > former function causes the latter to send the UIC_CMD_DME_HIBER_ENTER > command. Although UIC_CMD_DME_HIBER_ENTER causes the link to enter the > hibernation state, the code in ufshcd_uic_pwr_ctrl() for re-enabling > interrupts causes the UFS host controller that I'm testing to exit the > hibernation state. > >> Anyway, accessing the UFSHCI host controller registers space somehow >> affected the M-PHY link state? If my understanding is correct, it >> seems like a hardware issue that we are trying to work around? > > Yes, this is a workaround particular behavior of a particular UFS > controller. Thank you for the clarification, Bart. I am just curious about providing workaround for a hardware issue in the ufs core driver. Sometimes I notice the community is not accepting such a change and push the change to be implemented in the vendor/platform drivers. Now about your workaround, I have the same concern as Bean. For a ufshcd_uic_pwr_ctrl() command, i.e PMC, hibern8_enter/exit() commands, you will get 2 ufshcd_uic_cmd_compl() interrupts or 1 uic completion interrupt with 2 status bits set at once. a. UIC_COMMAND_COMPL is set b. and one of these bits UIC_POWER_MODE || UIC_HIBERNATE_EXIT || UIC_HIBERNATE_ENTER is set, depending on the completed uic command. In your proposed change to ufshcd_uic_cmd_compl(), you are signalling both complete(&cmd->done) and complete(hba->uic_async_done) for a single ufshcd_uic_pwr_ctrl() command which can cause issues. Thanks, Bao > > Thanks, > > Bart. >