From: Hannes Reinecke <hare@suse.de>
To: Bart Van Assche <bvanassche@acm.org>,
"Martin K . Petersen" <martin.petersen@oracle.com>,
"James E . J . Bottomley" <jejb@linux.vnet.ibm.com>
Cc: linux-scsi@vger.kernel.org, Daniel Wagner <dwagner@suse.de>,
Himanshu Madhani <himanshu.madhani@oracle.com>,
Nilesh Javali <njavali@marvell.com>,
Quinn Tran <qutran@marvell.com>, Martin Wilck <mwilck@suse.com>,
Roman Bolshakov <r.bolshakov@yadro.com>
Subject: Re: [PATCH v5 10/15] qla2xxx: Fix the code that reads from mailbox registers
Date: Tue, 12 May 2020 08:17:33 +0200 [thread overview]
Message-ID: <3def1366-2e63-173e-2664-44229b6f79ec@suse.de> (raw)
In-Reply-To: <20200511200946.7675-11-bvanassche@acm.org>
On 5/11/20 10:09 PM, Bart Van Assche wrote:
> Make the MMIO accessors strongly typed such that the compiler checks whether
> the accessor function is used that matches the register width. Fix those
> MMIO accesses where another number of bits was read or written than the size
> of the register.
>
> Reviewed-by: Daniel Wagner <dwagner@suse.de>
> Reviewed-by: Himanshu Madhani <himanshu.madhani@oracle.com>
> Reviewed-by: Hannes Reinecke <hare@suse.de>
> Cc: Nilesh Javali <njavali@marvell.com>
> Cc: Quinn Tran <qutran@marvell.com>
> Cc: Martin Wilck <mwilck@suse.com>
> Cc: Roman Bolshakov <r.bolshakov@yadro.com>
> Signed-off-by: Bart Van Assche <bvanassche@acm.org>
> ---
> drivers/scsi/qla2xxx/qla_def.h | 53 +++++++++++++++++++++++++++------
> drivers/scsi/qla2xxx/qla_init.c | 6 ++--
> drivers/scsi/qla2xxx/qla_iocb.c | 2 +-
> drivers/scsi/qla2xxx/qla_isr.c | 4 +--
> drivers/scsi/qla2xxx/qla_mbx.c | 2 +-
> drivers/scsi/qla2xxx/qla_mr.c | 26 ++++++++--------
> drivers/scsi/qla2xxx/qla_nx.c | 4 +--
> drivers/scsi/qla2xxx/qla_os.c | 2 +-
> 8 files changed, 67 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/scsi/qla2xxx/qla_def.h b/drivers/scsi/qla2xxx/qla_def.h
> index 5ca46b15ca3c..4b02b48af85d 100644
> --- a/drivers/scsi/qla2xxx/qla_def.h
> +++ b/drivers/scsi/qla2xxx/qla_def.h
> @@ -128,15 +128,50 @@ static inline uint32_t make_handle(uint16_t x, uint16_t y)
> * I/O register
> */
>
> -#define RD_REG_BYTE(addr) readb(addr)
> -#define RD_REG_WORD(addr) readw(addr)
> -#define RD_REG_DWORD(addr) readl(addr)
> -#define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
> -#define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
> -#define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
> -#define WRT_REG_BYTE(addr, data) writeb(data, addr)
> -#define WRT_REG_WORD(addr, data) writew(data, addr)
> -#define WRT_REG_DWORD(addr, data) writel(data, addr)
> +static inline u8 RD_REG_BYTE(const volatile u8 __iomem *addr)
> +{
> + return readb(addr);
> +}
> +
> +static inline u16 RD_REG_WORD(const volatile __le16 __iomem *addr)
> +{
> + return readw(addr);
> +}
> +
> +static inline u32 RD_REG_DWORD(const volatile __le32 __iomem *addr)
> +{
> + return readl(addr);
> +}
> +
> +static inline u8 RD_REG_BYTE_RELAXED(const volatile u8 __iomem *addr)
> +{
> + return readb_relaxed(addr);
> +}
> +
> +static inline u16 RD_REG_WORD_RELAXED(const volatile __le16 __iomem *addr)
> +{
> + return readw_relaxed(addr);
> +}
> +
> +static inline u32 RD_REG_DWORD_RELAXED(const volatile __le32 __iomem *addr)
> +{
> + return readl_relaxed(addr);
> +}
> +
> +static inline void WRT_REG_BYTE(volatile u8 __iomem *addr, u8 data)
> +{
> + return writeb(data, addr);
> +}
> +
> +static inline void WRT_REG_WORD(volatile __le16 __iomem *addr, u16 data)
> +{
> + return writew(data, addr);
> +}
> +
> +static inline void WRT_REG_DWORD(volatile __le32 __iomem *addr, u32 data)
> +{
> + return writel(data, addr);
> +}
>
> /*
> * ISP83XX specific remote register addresses
> diff --git a/drivers/scsi/qla2xxx/qla_init.c b/drivers/scsi/qla2xxx/qla_init.c
> index f8fe0334571f..a1018f5f53de 100644
> --- a/drivers/scsi/qla2xxx/qla_init.c
> +++ b/drivers/scsi/qla2xxx/qla_init.c
> @@ -2219,7 +2219,7 @@ qla2x00_initialize_adapter(scsi_qla_host_t *vha)
>
> /* Check for secure flash support */
> if (IS_QLA28XX(ha)) {
> - if (RD_REG_DWORD(®->mailbox12) & BIT_0)
> + if (RD_REG_WORD(®->mailbox12) & BIT_0)
> ha->flags.secure_adapter = 1;
> ql_log(ql_log_info, vha, 0xffff, "Secure Adapter: %s\n",
> (ha->flags.secure_adapter) ? "Yes" : "No");
> @@ -2780,7 +2780,7 @@ qla24xx_reset_risc(scsi_qla_host_t *vha)
> ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017f,
> "HCCR: 0x%x, MailBox0 Status 0x%x\n",
> RD_REG_DWORD(®->hccr),
> - RD_REG_DWORD(®->mailbox0));
> + RD_REG_WORD(®->mailbox0));
>
> /* Wait for soft-reset to complete. */
> RD_REG_DWORD(®->ctrl_status);
> @@ -4098,7 +4098,7 @@ qla24xx_config_rings(struct scsi_qla_host *vha)
> }
>
> /* PCI posting */
> - RD_REG_DWORD(&ioreg->hccr);
> + RD_REG_WORD(&ioreg->hccr);
> }
>
> /**
> diff --git a/drivers/scsi/qla2xxx/qla_iocb.c b/drivers/scsi/qla2xxx/qla_iocb.c
> index 182bd68c79ac..4d8039fc02e7 100644
> --- a/drivers/scsi/qla2xxx/qla_iocb.c
> +++ b/drivers/scsi/qla2xxx/qla_iocb.c
> @@ -2268,7 +2268,7 @@ __qla2x00_alloc_iocbs(struct qla_qpair *qpair, srb_t *sp)
> IS_QLA28XX(ha))
> cnt = RD_REG_DWORD(®->isp25mq.req_q_out);
> else if (IS_P3P_TYPE(ha))
> - cnt = RD_REG_DWORD(®->isp82.req_q_out);
> + cnt = RD_REG_DWORD(reg->isp82.req_q_out);
> else if (IS_FWI2_CAPABLE(ha))
> cnt = RD_REG_DWORD(®->isp24.req_q_out);
> else if (IS_QLAFX00(ha))
WTF?
Is 'isp82.req_q_out' a pointer, but the others are not?
This really looks dodgy...
Cheers,
Hannes
--
Dr. Hannes Reinecke Teamlead Storage & Networking
hare@suse.de +49 911 74053 688
SUSE Software Solutions GmbH, Maxfeldstr. 5, 90409 Nürnberg
HRB 36809 (AG Nürnberg), Geschäftsführer: Felix Imendörffer
next prev parent reply other threads:[~2020-05-12 6:17 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-11 20:09 [PATCH v5 00/15] Fix qla2xxx endianness annotations Bart Van Assche
2020-05-11 20:09 ` [PATCH v5 01/15] qla2xxx: Fix spelling of a variable name Bart Van Assche
2020-05-11 20:09 ` [PATCH v5 02/15] qla2xxx: Suppress two recently introduced compiler warnings Bart Van Assche
2020-05-11 20:09 ` [PATCH v5 03/15] qla2xxx: Simplify the functions for dumping firmware Bart Van Assche
2020-05-11 20:09 ` [PATCH v5 04/15] qla2xxx: Sort BUILD_BUG_ON() statements alphabetically Bart Van Assche
2020-05-11 20:09 ` [PATCH v5 05/15] qla2xxx: Add more BUILD_BUG_ON() statements Bart Van Assche
2020-05-11 20:09 ` [PATCH v5 06/15] qla2xxx: Make a gap in struct qla2xxx_offld_chain explicit Bart Van Assche
2020-05-11 20:09 ` [PATCH v5 07/15] qla2xxx: Increase the size of struct qla_fcp_prio_cfg to FCP_PRIO_CFG_SIZE Bart Van Assche
2020-05-11 20:09 ` [PATCH v5 08/15] qla2xxx: Change two hardcoded constants into offsetof() / sizeof() expressions Bart Van Assche
2020-05-11 20:09 ` [PATCH v5 09/15] qla2xxx: Use register names instead of register offsets Bart Van Assche
2020-05-12 6:11 ` Hannes Reinecke
2020-05-11 20:09 ` [PATCH v5 10/15] qla2xxx: Fix the code that reads from mailbox registers Bart Van Assche
2020-05-12 6:17 ` Hannes Reinecke [this message]
2020-05-12 15:55 ` Bart Van Assche
2020-05-11 20:09 ` [PATCH v5 11/15] qla2xxx: Change {RD,WRT}_REG_*() function names from upper case into lower case Bart Van Assche
2020-05-11 20:09 ` [PATCH v5 12/15] qla2xxx: Cast explicitly to uint16_t / uint32_t Bart Van Assche
2020-05-12 6:13 ` Hannes Reinecke
2020-05-11 20:09 ` [PATCH v5 13/15] qla2xxx: Use make_handle() instead of open-coding it Bart Van Assche
2020-05-11 20:09 ` [PATCH v5 14/15] qla2xxx: Fix endianness annotations in header files Bart Van Assche
2020-05-11 20:09 ` [PATCH v5 15/15] qla2xxx: Fix endianness annotations in source files Bart Van Assche
2020-05-12 16:44 ` [PATCH v5 00/15] Fix qla2xxx endianness annotations Martin K. Petersen
2020-05-13 1:29 ` Bart Van Assche
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