[PATCH v1 00/10] ufs: host: mediatek: Provide features and fixes in MediaTek platforms

[PATCH v1 00/10] ufs: host: mediatek: Provide features and fixes in MediaTek platforms

[peter.wang]

From: Peter Wang <peter.wang@mediatek.com>

This series fixes some defects and provide features in MediaTek UFS drivers.

Peter Wang (8):
  ufs: host: mediatek: Change return type to bool
  ufs: host: mediatek: Add memory barrier for ref-clk control
  ufs: host: mediatek: Change ref-clk timeout policy
  ufs: host: mediatek: Handle broken RTC based on DTS setting
  ufs: host: mediatek: Set IRQ affinity policy for MCQ mode
  ufs: host: mediatek: Add clock scaling query function
  ufs: host: mediatek: Support clock scaling with Vcore binding
  ufs: host: mediatek: Support FDE (AES) clock scaling

Naomi Chu (1):
  ufs: host: mediatek: Add DDR_EN setting

Alice Chao (1):
  ufs: host: mediatek: Add more UFSCHI hardware versions

 drivers/ufs/host/ufs-mediatek.c | 326 +++++++++++++++++++++++++++++---
 drivers/ufs/host/ufs-mediatek.h |  32 ++++
 2 files changed, 330 insertions(+), 28 deletions(-)

-- 
2.45.2

[PATCH v1 01/10] ufs: host: mediatek: Change return type to bool

[peter.wang]

From: Peter Wang <peter.wang@mediatek.com>

This patch updates the return type to bool for consistency
with the previous style.

Signed-off-by: Peter Wang <peter.wang@mediatek.com>
---
 drivers/ufs/host/ufs-mediatek.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index 182f58d0c9db..e56763e6c650 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -124,21 +124,21 @@ static bool ufs_mtk_is_tx_skew_fix(struct ufs_hba *hba)
 {
 	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
 
-	return (host->caps & UFS_MTK_CAP_TX_SKEW_FIX);
+	return !!(host->caps & UFS_MTK_CAP_TX_SKEW_FIX);
 }
 
 static bool ufs_mtk_is_rtff_mtcmos(struct ufs_hba *hba)
 {
 	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
 
-	return (host->caps & UFS_MTK_CAP_RTFF_MTCMOS);
+	return !!(host->caps & UFS_MTK_CAP_RTFF_MTCMOS);
 }
 
 static bool ufs_mtk_is_allow_vccqx_lpm(struct ufs_hba *hba)
 {
 	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
 
-	return (host->caps & UFS_MTK_CAP_ALLOW_VCCQX_LPM);
+	return !!(host->caps & UFS_MTK_CAP_ALLOW_VCCQX_LPM);
 }
 
 static void ufs_mtk_cfg_unipro_cg(struct ufs_hba *hba, bool enable)
-- 
2.45.2

[PATCH v1 02/10] ufs: host: mediatek: Add DDR_EN setting

[peter.wang]

From: Naomi Chu <naomi.chu@mediatek.com>

On MT6989 and later platforms, control of DDR_EN has been switched from
SPM to EMI. To prevent abnormal access to DRAM, it is necessary to wait
for 'ddren_ack' or assert 'ddren_urgent' after sending 'ddren_req'.

This patch introduces the DDR_EN configuration in the UFS initialization
flow, utilizing the assertion of 'ddren_urgent' to maintain performance.

Signed-off-by: Peter Wang <peter.wang@mediatek.com>
Signed-off-by: Naomi Chu <naomi.chu@mediatek.com>
Reviewed-by: Peter Wang <peter.wang@mediatek.com>
---
 drivers/ufs/host/ufs-mediatek.c |  7 +++++++
 drivers/ufs/host/ufs-mediatek.h | 12 ++++++++++++
 2 files changed, 19 insertions(+)

diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index e56763e6c650..3b3c3a1b2c42 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -267,6 +267,13 @@ static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba,
 		ufshcd_writel(hba,
 			      ufshcd_readl(hba, REG_UFS_XOUFS_CTRL) | 0x80,
 			      REG_UFS_XOUFS_CTRL);
+
+		/* DDR_EN setting */
+		if (host->ip_ver >= IP_VER_MT6989) {
+			ufshcd_rmwl(hba, UFS_MASK(0x7FFF, 8),
+				0x453000, REG_UFS_MMIO_OPT_CTRL_0);
+		}
+
 	}
 
 	return 0;
diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h
index 05d76a6bd772..e854801a00e8 100644
--- a/drivers/ufs/host/ufs-mediatek.h
+++ b/drivers/ufs/host/ufs-mediatek.h
@@ -192,4 +192,16 @@ struct ufs_mtk_host {
 /* MTK RTT support number */
 #define MTK_MAX_NUM_RTT 2
 
+/* UFS MTK ip version value */
+enum {
+	/* UFS 3.1 */
+	IP_VER_MT6878    = 0x10420200,
+
+	/* UFS 4.0 */
+	IP_VER_MT6897    = 0x10440000,
+	IP_VER_MT6989    = 0x10450000,
+
+	IP_VER_NONE      = 0xFFFFFFFF
+};
+
 #endif /* !_UFS_MEDIATEK_H */
-- 
2.45.2

[PATCH v1 03/10] ufs: host: mediatek: Add memory barrier for ref-clk control

[peter.wang]

From: Peter Wang <peter.wang@mediatek.com>

This patch adds a memory barrier to ensure that the ref-clk on/off control
register is fully written before it is read. This change is necessary to
maintain proper synchronization and prevent potential issues with register
access.

Signed-off-by: Peter Wang <peter.wang@mediatek.com>
---
 drivers/ufs/host/ufs-mediatek.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index 3b3c3a1b2c42..1e5cc88127b4 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -336,6 +336,12 @@ static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba, bool on)
 		ufshcd_writel(hba, REFCLK_RELEASE, REG_UFS_REFCLK_CTRL);
 	}
 
+	/*
+	 * Make sure that ref-clk on/off control register
+	 * is writed done before read it.
+	 */
+	mb();
+
 	/* Wait for ack */
 	timeout = ktime_add_us(ktime_get(), REFCLK_REQ_TIMEOUT_US);
 	do {
-- 
2.45.2

[PATCH v1 04/10] ufs: host: mediatek: Change ref-clk timeout policy

[peter.wang]

From: Peter Wang <peter.wang@mediatek.com>

This patch updates the timeout policy for ref-clk control.

- If a clock-on operation times out, it is assumed that the clock is
  off. The system will notify TFA to perform clock-off settings.
- If a clock-off operation times out, it is assumed that the clock
  will eventually turn off. The 'ref_clk_enabled' flag is set directly

Signed-off-by: Peter Wang <peter.wang@mediatek.com>
---
 drivers/ufs/host/ufs-mediatek.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index 1e5cc88127b4..b4d063ade0ec 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -357,7 +357,16 @@ static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba, bool on)
 
 	dev_err(hba->dev, "missing ack of refclk req, reg: 0x%x\n", value);
 
-	ufs_mtk_ref_clk_notify(host->ref_clk_enabled, POST_CHANGE, res);
+	/*
+	 * If clock on timeout, assume clock is off, notify tfa do clock
+	 * off setting.(keep DIFN disable, release resource)
+	 * If clock off timeout, assume clock will off finally,
+	 * set ref_clk_enabled directly.(keep DIFN disable, keep resource)
+	 */
+	if (on)
+		ufs_mtk_ref_clk_notify(false, POST_CHANGE, res);
+	else
+		host->ref_clk_enabled = false;
 
 	return -ETIMEDOUT;
 
-- 
2.45.2

[PATCH v1 05/10] ufs: host: mediatek: Handle broken RTC based on DTS setting

[peter.wang]

From: Peter Wang <peter.wang@mediatek.com>

This patch introduces a mechanism to handle broken RTC by checking
the DTS setting. The configuration is specifically required for
legacy platform.

Signed-off-by: Peter Wang <peter.wang@mediatek.com>
---
 drivers/ufs/host/ufs-mediatek.c | 8 +++++++-
 drivers/ufs/host/ufs-mediatek.h | 2 ++
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index b4d063ade0ec..87c58f482f6e 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -685,6 +685,9 @@ static void ufs_mtk_init_host_caps(struct ufs_hba *hba)
 	if (of_property_read_bool(np, "mediatek,ufs-rtff-mtcmos"))
 		host->caps |= UFS_MTK_CAP_RTFF_MTCMOS;
 
+	if (of_property_read_bool(np, "mediatek,ufs-broken-rtc"))
+		host->caps |= UFS_MTK_CAP_MCQ_BROKEN_RTC;
+
 	dev_info(hba->dev, "caps: 0x%x", host->caps);
 }
 
@@ -1041,8 +1044,11 @@ static int ufs_mtk_init(struct ufs_hba *hba)
 	shost->rpm_autosuspend_delay = MTK_RPM_AUTOSUSPEND_DELAY_MS;
 
 	hba->quirks |= UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL;
+
 	hba->quirks |= UFSHCD_QUIRK_MCQ_BROKEN_INTR;
-	hba->quirks |= UFSHCD_QUIRK_MCQ_BROKEN_RTC;
+	if (host->caps & UFS_MTK_CAP_MCQ_BROKEN_RTC)
+		hba->quirks |= UFSHCD_QUIRK_MCQ_BROKEN_RTC;
+
 	hba->vps->wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(80);
 
 	if (host->caps & UFS_MTK_CAP_DISABLE_AH8)
diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h
index e854801a00e8..16126a11195e 100644
--- a/drivers/ufs/host/ufs-mediatek.h
+++ b/drivers/ufs/host/ufs-mediatek.h
@@ -133,6 +133,8 @@ enum ufs_mtk_host_caps {
 	UFS_MTK_CAP_DISABLE_MCQ                = 1 << 8,
 	/* Control MTCMOS with RTFF */
 	UFS_MTK_CAP_RTFF_MTCMOS                = 1 << 9,
+
+	UFS_MTK_CAP_MCQ_BROKEN_RTC             = 1 << 10,
 };
 
 struct ufs_mtk_crypt_cfg {
-- 
2.45.2

[PATCH v1 06/10] ufs: host: mediatek: Set IRQ affinity policy for MCQ mode

[peter.wang]

From: Peter Wang <peter.wang@mediatek.com>

This patch sets the IRQ affinity for MCQ mode to improve
performance. Specifically, it migrates the IRQ from CPU0 to
CPU3 to enhance IRQ handling efficiency.

Signed-off-by: Peter Wang <peter.wang@mediatek.com>
---
 drivers/ufs/host/ufs-mediatek.c | 47 +++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index 87c58f482f6e..fb3b93f8fed0 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -804,6 +804,46 @@ static int ufs_mtk_setup_clocks(struct ufs_hba *hba, bool on,
 	return ret;
 }
 
+static u32 ufs_mtk_mcq_get_irq(struct ufs_hba *hba, unsigned int cpu)
+{
+	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
+	struct blk_mq_tag_set *tag_set = &hba->host->tag_set;
+	struct blk_mq_queue_map	*map = &tag_set->map[HCTX_TYPE_DEFAULT];
+	unsigned int nr = map->nr_queues;
+	unsigned int q_index;
+
+	q_index = map->mq_map[cpu];
+	if (q_index > nr) {
+		dev_err(hba->dev, "hwq index %d exceed %d\n",
+			q_index, nr);
+		return MTK_MCQ_INVALID_IRQ;
+	}
+
+	return host->mcq_intr_info[q_index].irq;
+}
+
+static void ufs_mtk_mcq_set_irq_affinity(struct ufs_hba *hba, unsigned int cpu)
+{
+	unsigned int irq, _cpu;
+	int ret;
+
+	irq = ufs_mtk_mcq_get_irq(hba, cpu);
+	if (irq == MTK_MCQ_INVALID_IRQ) {
+		dev_err(hba->dev, "invalid irq. unable to bind irq to cpu%d", cpu);
+		return;
+	}
+
+	/* force migrate irq of cpu0 to cpu3 */
+	_cpu = (cpu == 0) ? 3 : cpu;
+	ret = irq_set_affinity(irq, cpumask_of(_cpu));
+	if (ret) {
+		dev_err(hba->dev, "set irq %d affinity to CPU %d failed\n",
+			irq, _cpu);
+		return;
+	}
+	dev_info(hba->dev, "set irq %d affinity to CPU: %d\n", irq, _cpu);
+}
+
 static void ufs_mtk_get_controller_version(struct ufs_hba *hba)
 {
 	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
@@ -1533,6 +1573,13 @@ static int ufs_mtk_apply_dev_quirks(struct ufs_hba *hba)
 {
 	struct ufs_dev_info *dev_info = &hba->dev_info;
 	u16 mid = dev_info->wmanufacturerid;
+	unsigned int cpu;
+
+	if (hba->mcq_enabled) {
+		/* Iterate all cpus to set affinity for mcq irqs */
+		for (cpu = 0; cpu < nr_cpu_ids; cpu++)
+			ufs_mtk_mcq_set_irq_affinity(hba, cpu);
+	}
 
 	if (mid == UFS_VENDOR_SAMSUNG) {
 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 6);
-- 
2.45.2

[PATCH v1 07/10] ufs: host: mediatek: Add more UFSCHI hardware versions

[peter.wang]

From: Alice Chao <alice.chao@mediatek.com>

This patch introduces a function for version control to distinguish
between new and old platforms. It updates the handling of hardware
IP versions, ensuring correct version comparisons by adjusting the
version format for specific projects.

Signed-off-by: Peter Wang <peter.wang@mediatek.com>
Signed-off-by: Alice Chao <alice.chao@mediatek.com>
Reviewed-by: Peter Wang <peter.wang@mediatek.com>
---
 drivers/ufs/host/ufs-mediatek.c | 47 ++++++++++++++++++++++++++++++++-
 drivers/ufs/host/ufs-mediatek.h | 12 +++++++++
 2 files changed, 58 insertions(+), 1 deletion(-)

diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index fb3b93f8fed0..f9f397c2a61c 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -844,6 +844,51 @@ static void ufs_mtk_mcq_set_irq_affinity(struct ufs_hba *hba, unsigned int cpu)
 	dev_info(hba->dev, "set irq %d affinity to CPU: %d\n", irq, _cpu);
 }
 
+static bool ufs_mtk_is_legacy_chipset(struct ufs_hba *hba, u32 hw_ip_ver)
+{
+	bool is_legacy = false;
+
+	switch (hw_ip_ver) {
+	case IP_LEGACY_VER_MT6893:
+	case IP_LEGACY_VER_MT6781:
+		/* can add other legacy chipset ID here accordingly */
+		is_legacy = true;
+		break;
+	default:
+		break;
+	}
+	dev_info(hba->dev, "legacy IP version - 0x%x, is legacy : %d", hw_ip_ver, is_legacy);
+
+	return is_legacy;
+}
+
+/*
+ * HW version format has been changed from 01MMmmmm to 1MMMmmmm, since
+ * project MT6878. In order to perform correct version comparison,
+ * version number is changed by SW for the following projects.
+ * IP_VER_MT6983	0x00360000 to 0x10360000
+ * IP_VER_MT6897	0x01440000 to 0x10440000
+ * IP_VER_MT6989	0x01450000 to 0x10450000
+ * IP_VER_MT6991	0x01460000 to 0x10460000
+ */
+static void ufs_mtk_get_hw_ip_version(struct ufs_hba *hba)
+{
+	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
+	u32 hw_ip_ver;
+
+	hw_ip_ver = ufshcd_readl(hba, REG_UFS_MTK_IP_VER);
+
+	if (((hw_ip_ver & (0xFF << 24)) == (0x1 << 24)) ||
+	    ((hw_ip_ver & (0xFF << 24)) == 0)) {
+		hw_ip_ver &= ~(0xFF << 24);
+		hw_ip_ver |= (0x1 << 28);
+	}
+
+	host->ip_ver = hw_ip_ver;
+
+	host->legacy_ip_ver = ufs_mtk_is_legacy_chipset(hba, hw_ip_ver);
+}
+
 static void ufs_mtk_get_controller_version(struct ufs_hba *hba)
 {
 	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
@@ -1118,7 +1163,7 @@ static int ufs_mtk_init(struct ufs_hba *hba)
 
 	ufs_mtk_setup_clocks(hba, true, POST_CHANGE);
 
-	host->ip_ver = ufshcd_readl(hba, REG_UFS_MTK_IP_VER);
+	ufs_mtk_get_hw_ip_version(hba);
 
 	goto out;
 
diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h
index 16126a11195e..8c488640d0fe 100644
--- a/drivers/ufs/host/ufs-mediatek.h
+++ b/drivers/ufs/host/ufs-mediatek.h
@@ -181,6 +181,7 @@ struct ufs_mtk_host {
 	u16 ref_clk_ungating_wait_us;
 	u16 ref_clk_gating_wait_us;
 	u32 ip_ver;
+	bool legacy_ip_ver;
 
 	bool mcq_set_intr;
 	bool is_mcq_intr_enabled;
@@ -197,13 +198,24 @@ struct ufs_mtk_host {
 /* UFS MTK ip version value */
 enum {
 	/* UFS 3.1 */
+	IP_VER_MT6983    = 0x10360000,
 	IP_VER_MT6878    = 0x10420200,
 
 	/* UFS 4.0 */
 	IP_VER_MT6897    = 0x10440000,
 	IP_VER_MT6989    = 0x10450000,
+	IP_VER_MT6899    = 0x10450100,
+	IP_VER_MT6991_A0 = 0x10460000,
+	IP_VER_MT6991_B0 = 0x10470000,
+	IP_VER_MT6993    = 0x10480000,
 
 	IP_VER_NONE      = 0xFFFFFFFF
 };
 
+enum ip_ver_legacy {
+	IP_LEGACY_VER_MT6781 = 0x10380000,
+	IP_LEGACY_VER_MT6879 = 0x10360000,
+	IP_LEGACY_VER_MT6893 = 0x20160706
+};
+
 #endif /* !_UFS_MEDIATEK_H */
-- 
2.45.2

[PATCH v1 08/10] ufs: host: mediatek: Add clock scaling query function

[peter.wang]

From: Peter Wang <peter.wang@mediatek.com>

This patch introduces a clock scaling readiness query function to
streamline the process of checking clock scaling parameters.
This function simplifies the code by encapsulating the logic
for determining if clock scaling is ready.

Signed-off-by: Peter Wang <peter.wang@mediatek.com>
---
 drivers/ufs/host/ufs-mediatek.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index f9f397c2a61c..f74ab5286c6e 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -141,6 +141,16 @@ static bool ufs_mtk_is_allow_vccqx_lpm(struct ufs_hba *hba)
 	return !!(host->caps & UFS_MTK_CAP_ALLOW_VCCQX_LPM);
 }
 
+static bool ufs_mtk_is_clk_scale_ready(struct ufs_hba *hba)
+{
+	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
+	struct ufs_mtk_clk *mclk = &host->mclk;
+
+	return mclk->ufs_sel_clki &&
+		mclk->ufs_sel_max_clki &&
+		mclk->ufs_sel_min_clki;
+}
+
 static void ufs_mtk_cfg_unipro_cg(struct ufs_hba *hba, bool enable)
 {
 	u32 tmp;
@@ -950,8 +960,7 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba)
 		}
 	}
 
-	if (!mclk->ufs_sel_clki || !mclk->ufs_sel_max_clki ||
-	    !mclk->ufs_sel_min_clki) {
+	if (!ufs_mtk_is_clk_scale_ready(hba)) {
 		hba->caps &= ~UFSHCD_CAP_CLK_SCALING;
 		dev_info(hba->dev,
 			 "%s: Clk-scaling not ready. Feature disabled.",
-- 
2.45.2

[PATCH v1 09/10] ufs: host: mediatek: Support clock scaling with Vcore binding

[peter.wang]

From: Peter Wang <peter.wang@mediatek.com>

This patch adds support for clock scaling with Vcore binding.
It includes the following changes:
1. Parses the DTS setting for Vcore voltage.
2. Sets the Vcore voltage to the DTS-specified value before scaling up.
3. Resets the Vcore voltage to the default setting after scaling down.

These changes ensure that the Vcore voltage is appropriately managed
during clock scaling operations to maintain system stability and
performance.

Signed-off-by: Peter Wang <peter.wang@mediatek.com>
---
 drivers/ufs/host/ufs-mediatek.c | 129 +++++++++++++++++++++++++++-----
 drivers/ufs/host/ufs-mediatek.h |   3 +
 2 files changed, 112 insertions(+), 20 deletions(-)

diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index f74ab5286c6e..28aba2f24dd3 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -940,6 +940,9 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba)
 	struct list_head *head = &hba->clk_list_head;
 	struct ufs_mtk_clk *mclk = &host->mclk;
 	struct ufs_clk_info *clki, *clki_tmp;
+	struct device *dev = hba->dev;
+	struct regulator *reg;
+	u32 volt;
 
 	/*
 	 * Find private clocks and store them in struct ufs_mtk_clk.
@@ -965,6 +968,35 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba)
 		dev_info(hba->dev,
 			 "%s: Clk-scaling not ready. Feature disabled.",
 			 __func__);
+		return;
+	}
+
+	/*
+	 * Default get vcore if dts have these settings.
+	 * No matter clock scaling support or not. (may disable by customer)
+	 */
+	reg = devm_regulator_get_optional(dev, "dvfsrc-vcore");
+	if (IS_ERR(reg)) {
+		dev_info(dev, "failed to get dvfsrc-vcore: %ld",
+			 PTR_ERR(reg));
+		return;
+	}
+
+	if (of_property_read_u32(dev->of_node, "clk-scale-up-vcore-min",
+				 &volt)) {
+		dev_info(dev, "failed to get clk-scale-up-vcore-min");
+		return;
+	}
+
+	host->mclk.reg_vcore = reg;
+	host->mclk.vcore_volt = volt;
+
+	/* If default boot is max gear, request vcore */
+	if (reg && volt && host->clk_scale_up) {
+		if (regulator_set_voltage(reg, volt, INT_MAX)) {
+			dev_info(hba->dev,
+				"Failed to set vcore to %d\n", volt);
+		}
 	}
 }
 
@@ -1133,6 +1165,7 @@ static int ufs_mtk_init(struct ufs_hba *hba)
 
 	/* Enable clk scaling*/
 	hba->caps |= UFSHCD_CAP_CLK_SCALING;
+	host->clk_scale_up = true; /* default is max freq */
 
 	/* Set runtime pm delay to replace default */
 	shost->rpm_autosuspend_delay = MTK_RPM_AUTOSUSPEND_DELAY_MS;
@@ -1727,24 +1760,25 @@ static void ufs_mtk_config_scaling_param(struct ufs_hba *hba,
 	hba->vps->ondemand_data.downdifferential = 20;
 }
 
-/**
- * ufs_mtk_clk_scale - Internal clk scaling operation
- *
- * MTK platform supports clk scaling by switching parent of ufs_sel(mux).
- * The ufs_sel downstream to ufs_ck which feeds directly to UFS hardware.
- * Max and min clocks rate of ufs_sel defined in dts should match rate of
- * "ufs_sel_max_src" and "ufs_sel_min_src" respectively.
- * This prevent changing rate of pll clock that is shared between modules.
- *
- * @hba: per adapter instance
- * @scale_up: True for scaling up and false for scaling down
- */
-static void ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up)
+static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up)
 {
 	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
 	struct ufs_mtk_clk *mclk = &host->mclk;
 	struct ufs_clk_info *clki = mclk->ufs_sel_clki;
-	int ret = 0;
+	struct regulator *reg;
+	int volt, ret = 0;
+	bool clk_bind_vcore = false;
+
+	if (!hba->clk_scaling.is_initialized)
+		return;
+
+	if (!clki)
+		return;
+
+	reg = host->mclk.reg_vcore;
+	volt = host->mclk.vcore_volt;
+	if (reg && volt != 0)
+		clk_bind_vcore = true;
 
 	ret = clk_prepare_enable(clki->clk);
 	if (ret) {
@@ -1754,20 +1788,75 @@ static void ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up)
 	}
 
 	if (scale_up) {
+		if (clk_bind_vcore) {
+			ret = regulator_set_voltage(reg, volt, INT_MAX);
+			if (ret) {
+				dev_info(hba->dev,
+					"Failed to set vcore to %d\n", volt);
+				goto out;
+			}
+		}
+
 		ret = clk_set_parent(clki->clk, mclk->ufs_sel_max_clki->clk);
-		clki->curr_freq = clki->max_freq;
+		if (ret) {
+			dev_info(hba->dev, "Failed to set clk mux, ret = %d\n",
+				ret);
+		}
 	} else {
 		ret = clk_set_parent(clki->clk, mclk->ufs_sel_min_clki->clk);
-		clki->curr_freq = clki->min_freq;
-	}
+		if (ret) {
+			dev_info(hba->dev, "Failed to set clk mux, ret = %d\n",
+				ret);
+			goto out;
+		}
 
-	if (ret) {
-		dev_info(hba->dev,
-			 "Failed to set ufs_sel_clki, ret: %d\n", ret);
+		if (clk_bind_vcore) {
+			ret = regulator_set_voltage(reg, 0, INT_MAX);
+			if (ret) {
+				dev_info(hba->dev,
+					"failed to set vcore to MIN\n");
+			}
+		}
 	}
 
+out:
 	clk_disable_unprepare(clki->clk);
+}
+
+/**
+ * ufs_mtk_clk_scale - Internal clk scaling operation
+ *
+ * MTK platform supports clk scaling by switching parent of ufs_sel(mux).
+ * The ufs_sel downstream to ufs_ck which feeds directly to UFS hardware.
+ * Max and min clocks rate of ufs_sel defined in dts should match rate of
+ * "ufs_sel_max_src" and "ufs_sel_min_src" respectively.
+ * This prevent changing rate of pll clock that is shared between modules.
+ *
+ * @hba: per adapter instance
+ * @scale_up: True for scaling up and false for scaling down
+ */
+static void ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up)
+{
+	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
+	struct ufs_mtk_clk *mclk = &host->mclk;
+	struct ufs_clk_info *clki = mclk->ufs_sel_clki;
+
+	if (host->clk_scale_up == scale_up)
+		goto out;
+
+	if (scale_up)
+		_ufs_mtk_clk_scale(hba, true);
+	else
+		_ufs_mtk_clk_scale(hba, false);
 
+	host->clk_scale_up = scale_up;
+
+	/* Must always set before clk_set_rate() */
+	if (scale_up)
+		clki->curr_freq = clki->max_freq;
+	else
+		clki->curr_freq = clki->min_freq;
+out:
 	trace_ufs_mtk_clk_scale(clki->name, scale_up, clk_get_rate(clki->clk));
 }
 
diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h
index 8c488640d0fe..1395c65b46fe 100644
--- a/drivers/ufs/host/ufs-mediatek.h
+++ b/drivers/ufs/host/ufs-mediatek.h
@@ -149,6 +149,8 @@ struct ufs_mtk_clk {
 	struct ufs_clk_info *ufs_sel_clki; /* Mux */
 	struct ufs_clk_info *ufs_sel_max_clki; /* Max src */
 	struct ufs_clk_info *ufs_sel_min_clki; /* Min src */
+	struct regulator *reg_vcore;
+	int vcore_volt;
 };
 
 struct ufs_mtk_hw_ver {
@@ -178,6 +180,7 @@ struct ufs_mtk_host {
 	bool mphy_powered_on;
 	bool unipro_lpm;
 	bool ref_clk_enabled;
+	bool clk_scale_up;
 	u16 ref_clk_ungating_wait_us;
 	u16 ref_clk_gating_wait_us;
 	u32 ip_ver;
-- 
2.45.2

[PATCH v1 10/10] ufs: host: mediatek: Support FDE (AES) clock scaling

[peter.wang]

From: Peter Wang <peter.wang@mediatek.com>

This patch adds support for scaling the FDE (AES) clock to achieve higher
performance, particularly for HS-G5. The implementation includes:
1. Parsing DTS settings for FDE min/max mux.
2. Scaling up the FDE clock when required for enhanced performance.

These changes ensure that the FDE clock can be dynamically adjusted
based on performance needs, leveraging DTS configurations.

Signed-off-by: Peter Wang <peter.wang@mediatek.com>
---
 drivers/ufs/host/ufs-mediatek.c | 54 ++++++++++++++++++++++++++++++++-
 drivers/ufs/host/ufs-mediatek.h |  3 ++
 2 files changed, 56 insertions(+), 1 deletion(-)

diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index 28aba2f24dd3..bcebbd42baab 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -960,9 +960,23 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba)
 			host->mclk.ufs_sel_min_clki = clki;
 			clk_disable_unprepare(clki->clk);
 			list_del(&clki->list);
+		} else if (!strcmp(clki->name, "ufs_fde")) {
+			host->mclk.ufs_fde_clki = clki;
+		} else if (!strcmp(clki->name, "ufs_fde_max_src")) {
+			host->mclk.ufs_fde_max_clki = clki;
+			clk_disable_unprepare(clki->clk);
+			list_del(&clki->list);
+		} else if (!strcmp(clki->name, "ufs_fde_min_src")) {
+			host->mclk.ufs_fde_min_clki = clki;
+			clk_disable_unprepare(clki->clk);
+			list_del(&clki->list);
 		}
 	}
 
+	list_for_each_entry(clki, head, list) {
+		dev_info(hba->dev, "clk \"%s\" present", clki->name);
+	}
+
 	if (!ufs_mtk_is_clk_scale_ready(hba)) {
 		hba->caps &= ~UFSHCD_CAP_CLK_SCALING;
 		dev_info(hba->dev,
@@ -1765,14 +1779,16 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up)
 	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
 	struct ufs_mtk_clk *mclk = &host->mclk;
 	struct ufs_clk_info *clki = mclk->ufs_sel_clki;
+	struct ufs_clk_info *fde_clki = mclk->ufs_fde_clki;
 	struct regulator *reg;
 	int volt, ret = 0;
 	bool clk_bind_vcore = false;
+	bool clk_fde_scale = false;
 
 	if (!hba->clk_scaling.is_initialized)
 		return;
 
-	if (!clki)
+	if (!clki || !fde_clki)
 		return;
 
 	reg = host->mclk.reg_vcore;
@@ -1780,6 +1796,9 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up)
 	if (reg && volt != 0)
 		clk_bind_vcore = true;
 
+	if (mclk->ufs_fde_max_clki && mclk->ufs_fde_min_clki)
+		clk_fde_scale = true;
+
 	ret = clk_prepare_enable(clki->clk);
 	if (ret) {
 		dev_info(hba->dev,
@@ -1787,6 +1806,15 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up)
 		return;
 	}
 
+	if (clk_fde_scale) {
+		ret = clk_prepare_enable(fde_clki->clk);
+		if (ret) {
+			dev_info(hba->dev,
+				 "fde clk_prepare_enable() fail, ret: %d\n", ret);
+			return;
+		}
+	}
+
 	if (scale_up) {
 		if (clk_bind_vcore) {
 			ret = regulator_set_voltage(reg, volt, INT_MAX);
@@ -1802,7 +1830,28 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up)
 			dev_info(hba->dev, "Failed to set clk mux, ret = %d\n",
 				ret);
 		}
+
+		if (clk_fde_scale) {
+			ret = clk_set_parent(fde_clki->clk,
+				mclk->ufs_fde_max_clki->clk);
+			if (ret) {
+				dev_info(hba->dev,
+					"Failed to set fde clk mux, ret = %d\n",
+					ret);
+			}
+		}
 	} else {
+		if (clk_fde_scale) {
+			ret = clk_set_parent(fde_clki->clk,
+				mclk->ufs_fde_min_clki->clk);
+			if (ret) {
+				dev_info(hba->dev,
+					"Failed to set fde clk mux, ret = %d\n",
+					ret);
+				goto out;
+			}
+		}
+
 		ret = clk_set_parent(clki->clk, mclk->ufs_sel_min_clki->clk);
 		if (ret) {
 			dev_info(hba->dev, "Failed to set clk mux, ret = %d\n",
@@ -1821,6 +1870,9 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up)
 
 out:
 	clk_disable_unprepare(clki->clk);
+
+	if (clk_fde_scale)
+		clk_disable_unprepare(fde_clki->clk);
 }
 
 /**
diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h
index 1395c65b46fe..997da391d0a0 100644
--- a/drivers/ufs/host/ufs-mediatek.h
+++ b/drivers/ufs/host/ufs-mediatek.h
@@ -149,6 +149,9 @@ struct ufs_mtk_clk {
 	struct ufs_clk_info *ufs_sel_clki; /* Mux */
 	struct ufs_clk_info *ufs_sel_max_clki; /* Max src */
 	struct ufs_clk_info *ufs_sel_min_clki; /* Min src */
+	struct ufs_clk_info *ufs_fde_clki; /* Mux */
+	struct ufs_clk_info *ufs_fde_max_clki; /* Max src */
+	struct ufs_clk_info *ufs_fde_min_clki; /* Min src */
 	struct regulator *reg_vcore;
 	int vcore_volt;
 };
-- 
2.45.2

Re: [PATCH v1 00/10] ufs: host: mediatek: Provide features and fixes in MediaTek platforms

[Chun-Hung Wu (巫駿宏)]

On Wed, 2025-07-16 at 14:25 +0800, peter.wang@mediatek.com wrote:
> From: Peter Wang <peter.wang@mediatek.com>
> 
> This series fixes some defects and provide features in MediaTek UFS
> drivers.
> 
> Peter Wang (8):
>   ufs: host: mediatek: Change return type to bool
>   ufs: host: mediatek: Add memory barrier for ref-clk control
>   ufs: host: mediatek: Change ref-clk timeout policy
>   ufs: host: mediatek: Handle broken RTC based on DTS setting
>   ufs: host: mediatek: Set IRQ affinity policy for MCQ mode
>   ufs: host: mediatek: Add clock scaling query function
>   ufs: host: mediatek: Support clock scaling with Vcore binding
>   ufs: host: mediatek: Support FDE (AES) clock scaling
> 
> Naomi Chu (1):
>   ufs: host: mediatek: Add DDR_EN setting
> 
> Alice Chao (1):
>   ufs: host: mediatek: Add more UFSCHI hardware versions
> 
>  drivers/ufs/host/ufs-mediatek.c | 326 +++++++++++++++++++++++++++++-
> --
>  drivers/ufs/host/ufs-mediatek.h |  32 ++++
>  2 files changed, 330 insertions(+), 28 deletions(-)
> 

Reviewed-by: Chun-Hung Wu<chun-hung.wu@mediatek.com>

Re: [PATCH v1 01/10] ufs: host: mediatek: Change return type to bool

[Bart Van Assche]

On 7/15/25 11:25 PM, peter.wang@mediatek.com wrote:
> This patch updates the return type to bool for consistency
> with the previous style.

What previous style?

Please follow the style that is used elsewhere in the Linux kernel and
do *not* introduce any unnecessary explicit conversions to bool.

Bart.

Re: [PATCH v1 02/10] ufs: host: mediatek: Add DDR_EN setting

[Bart Van Assche]

On 7/15/25 11:25 PM, peter.wang@mediatek.com wrote:
> On MT6989 and later platforms, control of DDR_EN has been switched from
> SPM to EMI. To prevent abnormal access to DRAM, it is necessary to wait
> for 'ddren_ack' or assert 'ddren_urgent' after sending 'ddren_req'.
> 
> This patch introduces the DDR_EN configuration in the UFS initialization
> flow, utilizing the assertion of 'ddren_urgent' to maintain performance.

What is SPM? What is EMI? What is DDR_EN? Please expand these acronyms.

> +/* UFS MTK ip version value */
> +enum {
> +	/* UFS 3.1 */
> +	IP_VER_MT6878    = 0x10420200,
> +
> +	/* UFS 4.0 */
> +	IP_VER_MT6897    = 0x10440000,
> +	IP_VER_MT6989    = 0x10450000,
> +
> +	IP_VER_NONE      = 0xFFFFFFFF
> +};

How can MediaTek IP versions be related to the UFS standard? Should
"UFS" perhaps be changed into "UFSHCI" in the above comments?

Thanks,

Bart.

Re: [PATCH v1 03/10] ufs: host: mediatek: Add memory barrier for ref-clk control

[Bart Van Assche]

On 7/15/25 11:25 PM, peter.wang@mediatek.com wrote:
> +	/*
> +	 * Make sure that ref-clk on/off control register
> +	 * is writed done before read it.
> +	 */
> +	mb();

A memory barrier doesn't guarantee that an MMIO write has been
completed. A memory barrier enforces ordering of MMIO writes but does
not guarantee completion of MMIO writes. What you need is an MMIO read.
See e.g. commit 4bf3855497b6 ("scsi: ufs: core: Perform read back after 
disabling UIC_COMMAND_COMPL").

Bart.

Re: [PATCH v1 06/10] ufs: host: mediatek: Set IRQ affinity policy for MCQ mode

[Bart Van Assche]

On 7/15/25 11:25 PM, peter.wang@mediatek.com wrote:
> This patch sets the IRQ affinity for MCQ mode to improve
> performance. Specifically, it migrates the IRQ from CPU0 to
> CPU3 to enhance IRQ handling efficiency.

IRQ affinity can and should be set from userspace.

Bart.

Re: [PATCH v1 08/10] ufs: host: mediatek: Add clock scaling query function

[kernel test robot]

Hi,

kernel test robot noticed the following build warnings:

[auto build test WARNING on jejb-scsi/for-next]
[also build test WARNING on mkp-scsi/for-next linus/master v6.16-rc6 next-20250716]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/peter-wang-mediatek-com/ufs-host-mediatek-Change-return-type-to-bool/20250716-184239
base:   https://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi.git for-next
patch link:    https://lore.kernel.org/r/20250716062830.3712487-9-peter.wang%40mediatek.com
patch subject: [PATCH v1 08/10] ufs: host: mediatek: Add clock scaling query function
config: arm-allmodconfig (https://download.01.org/0day-ci/archive/20250717/202507171210.1ZvrCG7u-lkp@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 15.1.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250717/202507171210.1ZvrCG7u-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202507171210.1ZvrCG7u-lkp@intel.com/

All warnings (new ones prefixed by >>):

   drivers/ufs/host/ufs-mediatek.c: In function 'ufs_mtk_init_clocks':
>> drivers/ufs/host/ufs-mediatek.c:941:29: warning: unused variable 'mclk' [-Wunused-variable]
     941 |         struct ufs_mtk_clk *mclk = &host->mclk;
         |                             ^~~~


vim +/mclk +941 drivers/ufs/host/ufs-mediatek.c

2c89e41326b16e drivers/scsi/ufs/ufs-mediatek.c Stanley Chu 2021-05-31  931  
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  932  /**
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  933   * ufs_mtk_init_clocks - Init mtk driver private clocks
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  934   *
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  935   * @hba: per adapter instance
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  936   */
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  937  static void ufs_mtk_init_clocks(struct ufs_hba *hba)
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  938  {
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  939  	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  940  	struct list_head *head = &hba->clk_list_head;
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03 @941  	struct ufs_mtk_clk *mclk = &host->mclk;
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  942  	struct ufs_clk_info *clki, *clki_tmp;
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  943  
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  944  	/*
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  945  	 * Find private clocks and store them in struct ufs_mtk_clk.
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  946  	 * Remove "ufs_sel_min_src" and "ufs_sel_min_src" from list to avoid
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  947  	 * being switched on/off in clock gating.
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  948  	 */
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  949  	list_for_each_entry_safe(clki, clki_tmp, head, list) {
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  950  		if (!strcmp(clki->name, "ufs_sel")) {
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  951  			host->mclk.ufs_sel_clki = clki;
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  952  		} else if (!strcmp(clki->name, "ufs_sel_max_src")) {
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  953  			host->mclk.ufs_sel_max_clki = clki;
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  954  			clk_disable_unprepare(clki->clk);
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  955  			list_del(&clki->list);
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  956  		} else if (!strcmp(clki->name, "ufs_sel_min_src")) {
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  957  			host->mclk.ufs_sel_min_clki = clki;
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  958  			clk_disable_unprepare(clki->clk);
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  959  			list_del(&clki->list);
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  960  		}
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  961  	}
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  962  
37e94f8b8c2c07 drivers/ufs/host/ufs-mediatek.c Peter Wang  2025-07-16  963  	if (!ufs_mtk_is_clk_scale_ready(hba)) {
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  964  		hba->caps &= ~UFSHCD_CAP_CLK_SCALING;
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  965  		dev_info(hba->dev,
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  966  			 "%s: Clk-scaling not ready. Feature disabled.",
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  967  			 __func__);
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  968  	}
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  969  }
b7dbc686f60b28 drivers/ufs/host/ufs-mediatek.c Po-Wen Kao  2022-08-03  970  

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH v1 01/10] ufs: host: mediatek: Change return type to bool

[Peter Wang (王信友)]

On Wed, 2025-07-16 at 08:19 -0700, Bart Van Assche wrote:
> 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> On 7/15/25 11:25 PM, peter.wang@mediatek.com wrote:
> > This patch updates the return type to bool for consistency
> > with the previous style.
> 
> What previous style?
> 
> Please follow the style that is used elsewhere in the Linux kernel
> and
> do *not* introduce any unnecessary explicit conversions to bool.
> 
> Bart.


Hi Bart,

This is to be consistent with the usage earlier in mediatek.c, such as

static bool ufs_mtk_is_pmc_via_fastauto(struct ufs_hba *hba)
{
	struct ufs_mtk_host *host = ufshcd_get_variant(hba);

	return !!(host->caps & UFS_MTK_CAP_PMC_VIA_FASTAUTO);
}

Or do you suggest removing all the previous usages instead?

Thanks.
Peter

Re: [PATCH v1 02/10] ufs: host: mediatek: Add DDR_EN setting

[Peter Wang (王信友)]

On Wed, 2025-07-16 at 08:22 -0700, Bart Van Assche wrote:
> 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> On 7/15/25 11:25 PM, peter.wang@mediatek.com wrote:
> > On MT6989 and later platforms, control of DDR_EN has been switched
> > from
> > SPM to EMI. To prevent abnormal access to DRAM, it is necessary to
> > wait
> > for 'ddren_ack' or assert 'ddren_urgent' after sending 'ddren_req'.
> > 
> > This patch introduces the DDR_EN configuration in the UFS
> > initialization
> > flow, utilizing the assertion of 'ddren_urgent' to maintain
> > performance.
> 
> What is SPM? What is EMI? What is DDR_EN? Please expand these
> acronyms.
> 

Hi Bart,

Sorry, this is confidential to MediaTek’s design, as ufs-mediatek.c
is code specific to the MediaTek UFS host. It does not involve common
or other host usages, so please allow us not to explain the design
details or abbreviations.


> > +/* UFS MTK ip version value */
> > +enum {
> > +     /* UFS 3.1 */
> > +     IP_VER_MT6878    = 0x10420200,
> > +
> > +     /* UFS 4.0 */
> > +     IP_VER_MT6897    = 0x10440000,
> > +     IP_VER_MT6989    = 0x10450000,
> > +
> > +     IP_VER_NONE      = 0xFFFFFFFF
> > +};
> 
> How can MediaTek IP versions be related to the UFS standard? Should
> "UFS" perhaps be changed into "UFSHCI" in the above comments?
> 
> Thanks,
> 
> Bart.


Sure, I will update the comment from "UFS" to "UFSHCI".

Thanks.
Peter

Re: [PATCH v1 03/10] ufs: host: mediatek: Add memory barrier for ref-clk control

[Peter Wang (王信友)]

On Wed, 2025-07-16 at 08:26 -0700, Bart Van Assche wrote:
> 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> On 7/15/25 11:25 PM, peter.wang@mediatek.com wrote:
> > +     /*
> > +      * Make sure that ref-clk on/off control register
> > +      * is writed done before read it.
> > +      */
> > +     mb();
> 
> A memory barrier doesn't guarantee that an MMIO write has been
> completed. A memory barrier enforces ordering of MMIO writes but does
> not guarantee completion of MMIO writes. What you need is an MMIO
> read.
> See e.g. commit 4bf3855497b6 ("scsi: ufs: core: Perform read back
> after
> disabling UIC_COMMAND_COMPL").
> 
> Bart.


Hi Bart,

Understood, this seems to be unnecessary code and will be removed
in the next version.

Thanks.
Peter

Re: [PATCH v1 06/10] ufs: host: mediatek: Set IRQ affinity policy for MCQ mode

[Peter Wang (王信友)]

On Wed, 2025-07-16 at 08:27 -0700, Bart Van Assche wrote:
> 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> On 7/15/25 11:25 PM, peter.wang@mediatek.com wrote:
> > This patch sets the IRQ affinity for MCQ mode to improve
> > performance. Specifically, it migrates the IRQ from CPU0 to
> > CPU3 to enhance IRQ handling efficiency.
> 
> IRQ affinity can and should be set from userspace.
> 
> Bart.


Hi Bart,

"IRQ affinity can be set from userspace." 
=> This is correct.

"IRQ affinity should be set from userspace." 
=> I have some doubts about this statement.
Is there any documentation that explains this?


As far as I understand,
This depends on the situation. By default, Linux automatically
distributes
IRQs across CPUs, which is sufficient for most systems. However, in
certain high-performance or special-use cases (such as for network
cards
or storage devices), manually setting IRQ affinity can improve
performance or reduce latency.

Thanks.
Peter

Re: [PATCH v1 01/10] ufs: host: mediatek: Change return type to bool

[Bart Van Assche]

On 7/16/25 11:37 PM, Peter Wang (王信友) wrote:
> Or do you suggest removing all the previous usages instead?

That would be appreciated!

Thanks,

Bart.

Re: [PATCH v1 06/10] ufs: host: mediatek: Set IRQ affinity policy for MCQ mode

[Bart Van Assche]

On 7/16/25 11:54 PM, Peter Wang (王信友) wrote:
> As far as I understand, This depends on the situation. By default,
> Linux automatically distributes IRQs across CPUs, which is
> sufficient for most systems. However, in certain high-performance or
> special-use cases (such as for network cards or storage devices),
> manually setting IRQ affinity can improve performance or reduce
> latency.

Hi Peter,

It would be great if it could be explained in the patch description why
the IRQ affinity changes happen from kernel space instead of from user
space.

Thanks,

Bart.