From: Xi Wang <xi.wang@gmail.com>
To: James Bottomley <James.Bottomley@HansenPartnership.com>
Cc: Xiangliang Yu <yuxiangl@marvell.com>,
linux-scsi@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/3] [SCSI] mvsas: fix shift in mvs_94xx_free_reg_set()
Date: Tue, 06 Nov 2012 15:55:49 -0500 [thread overview]
Message-ID: <50997955.10000@gmail.com> (raw)
In-Reply-To: <1352203618.2529.22.camel@dabdike>
On 11/6/12 7:06 AM, James Bottomley wrote:
>
> Why is this necessary? As I read the reg set assignment code, it finds
> a free bit in the 64 bit register and uses that ... which can never be
> greater than 64 so there's no need for the check.
This patch just tries to be more defensive for bit(reg_set) with a
broken reg_set value. I agree with you that it's not that necessary.
> The other two look OK (probably redone as a single patch with a stable
> tag), but I'd like the input of the mvs people since it seems with the
> current code, we only use 32 bit regsets and probably hang if we go over
> that. The bug fix is either to enable the full 64 if it works, or
> possibly cap at 32 ... what works with all released devices?
Thanks for reviewing. Yeah we'd better to wait for the input from
the mvs people.
- xi
next prev parent reply other threads:[~2012-11-06 20:55 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-11-05 19:53 [PATCH 0/3] [SCSI] mvsas: fix multiple shift issues Xi Wang
2012-11-05 19:53 ` [PATCH 1/3] [SCSI] mvsas: fix shift in mvs_94xx_assign_reg_set() Xi Wang
2012-11-05 19:53 ` [PATCH 2/3] [SCSI] mvsas: fix shift in mvs_94xx_free_reg_set() Xi Wang
2012-11-06 12:06 ` James Bottomley
2012-11-06 20:55 ` Xi Wang [this message]
2012-11-09 7:30 ` Xiangliang Yu
2012-11-09 13:44 ` Xi Wang
2012-11-16 7:39 ` Xiangliang Yu
2012-11-05 19:53 ` [PATCH 3/3] [SCSI] mvsas: fix shift in mv_ffc64() Xi Wang
2012-11-16 19:40 ` [PATCH v2] [SCSI] mvsas: fix undefined bit shift Xi Wang
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