From: "Chun-Hung Wu (巫駿宏)" <Chun-hung.Wu@mediatek.com>
To: "ebiggers@google.com" <ebiggers@google.com>,
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Cc: "Peter Wang (王信友)" <peter.wang@mediatek.com>,
"Eddie Huang (黃智傑)" <eddie.huang@mediatek.com>,
"Jiajie Hao (郝加节)" <jiajie.hao@mediatek.com>,
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Subject: Re: [PATCH v1 1/1] ufs: core: Add host quirk QUIRK_MCQ_EXPAND_QUEUE_SLOT
Date: Fri, 27 Oct 2023 03:27:13 +0000 [thread overview]
Message-ID: <53d7d12bc12237e5f86522faf09876ab08ef7592.camel@mediatek.com> (raw)
In-Reply-To: <3056c6d8-1e54-4954-9141-e0760a0d935a@acm.org>
On Wed, 2023-10-25 at 11:10 -0700, Bart Van Assche wrote:
>
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> On 10/25/23 01:56, Chun-Hung Wu wrote:
> > This quirk needs to be enabled if the host controller cannot
> > distinguish queue full or empty.
>
> From the UFSHCI 4.0 specification: "When the head and tail doorbells
> are
> equal, the queue is empty. [ ... ] When the head and tail doorbells
> are
> not equal, the queue contains queue entries."
>
> How is it possible that a host controller cannot distinguish queue
> full
> or queue empty? Which (head - tail) values cause trouble? More
> information is needed.
>
> Thanks,
>
> Bart.
>
From UFSHCI 4.0 spec "When the head and tail doorbells are equal, the
queue is empty. *Nothe that this definition means there will always be
one empty queue entry"
One of our platform does not keep one empty queue
entry for CQ full
case, that's why we need this patch to fix this corner case.
Thanks,
Chun-Hung
next prev parent reply other threads:[~2023-10-27 3:27 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-25 8:56 [PATCH v1 0/1] ufs: core: Add host quirk QUIRK_MCQ_EXPAND_QUEUE_SLOT Chun-Hung Wu
2023-10-25 8:56 ` [PATCH v1 1/1] " Chun-Hung Wu
2023-10-25 18:10 ` Bart Van Assche
2023-10-27 3:27 ` Chun-Hung Wu (巫駿宏) [this message]
2023-10-27 20:55 ` Bart Van Assche
2023-10-30 6:19 ` Chun-Hung Wu (巫駿宏)
2023-10-25 11:36 ` [PATCH v1 0/1] " Avri Altman
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