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From: zhangfei <zhangfei.gao@linaro.org>
To: Mark Rutland <mark.rutland@arm.com>, John Garry <john.garry@huawei.com>
Cc: JBottomley@odin.com, robh+dt@kernel.org, pawel.moll@arm.com,
	ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
	arnd@arndb.de, linux-scsi@vger.kernel.org,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linuxarm@huawei.com, john.garry2@mail.dcu.ie, hare@suse.de,
	xuwei5@hisilicon.com
Subject: Re: [PATCH v2 02/32] devicetree: bindings: scsi: HiSi SAS
Date: Tue, 27 Oct 2015 22:54:14 +0800	[thread overview]
Message-ID: <562F9016.50807@linaro.org> (raw)
In-Reply-To: <20151027143939.GG3091@leverpostej>



On 10/27/2015 10:39 PM, Mark Rutland wrote:
> On Tue, Oct 27, 2015 at 01:09:15PM +0000, John Garry wrote:
>> On 26/10/2015 14:45, Mark Rutland wrote:
>>> On Mon, Oct 26, 2015 at 10:14:33PM +0800, John Garry wrote:
>>>> Add devicetree bindings for HiSilicon SAS driver.
>>>>
>>>> Signed-off-by: John Garry <john.garry@huawei.com>
>>>> ---
>>>>   .../devicetree/bindings/scsi/hisilicon-sas.txt     | 70 ++++++++++++++++++++++
>>>>   1 file changed, 70 insertions(+)
>>>>   create mode 100644 Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
>>>> new file mode 100644
>>>> index 0000000..d1e7b2a
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
>>>> @@ -0,0 +1,70 @@
>>>> +* HiSilicon SAS controller
>>>> +
>>>> +The HiSilicon SAS controller supports SAS/SATA.
>>>> +
>>>> +Main node required properties:
>>>> +  - compatible : value should be as follows:
>>>> +	(a) "hisilicon,sas-controller-v1" for v1 of HiSilicon SAS controller IP
>>>> +  - reg : Address and length of the SAS register
>>>> +  - hisilicon,sas-syscon: phandle of syscon used for sas control
>>>> +  - ctrl-reg : offset to the following SAS control registers (in order):
>>>> +		- reset assert
>>>> +		- clock disable
>>>> +		- reset status
>>>> +		- reset de-assert
>>>> +		- clock enable
>>>
>>> This needs a better name, and it should probably be split up into
>>> several properties.
>>>
>>> However, it sounds like the syscon is actually a clock+reset
>>> controller, and should be modelled as such. It's not actually a part of
>>> the SAS controller as such.
>>
>> The syscon block is a general subsystem control block, and it is not
>> specifically only for controlling reset and enabling clocks (other
>> functions include serdes control, for example). It is also shared
>> with other peripherals.
>>
>> So we can remove the ctrl-reg property (since it is not part of the
>> SAS controller), and add the relevant syscon register offsets to the
>> "hisilicon,sas-syscon" property, like this:
>> hisilicon,sas-syscon = <&sas_ctrl0 0xa60 0x33c 0x5a30 0xa64 0x338>;
>>
>> Ok?
>
> It would be better to have each offset in a separate property.
>
These register are not used for different purpose.
Instead, they are all used for one purpose, reset the sas controller;
Though a bit complicated, the silicon has special requirement here.

So still prefer using the original method,
ctrl-reg = <0xa60 0x33c 0x5a30 0xa64 0x338>;
Since we can simply use of_property_read_u32_array.

Thanks


  reply	other threads:[~2015-10-27 14:54 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-26 14:14 [PATCH v2 00/32] HiSilicon SAS driver John Garry
2015-10-26 14:14 ` [PATCH v2 01/32] [SCSI] sas: centralise ssp frame information units John Garry
2015-10-26 14:14 ` [PATCH v2 02/32] devicetree: bindings: scsi: HiSi SAS John Garry
2015-10-26 14:45   ` Mark Rutland
2015-10-27 13:09     ` John Garry
2015-10-27 14:39       ` Mark Rutland
2015-10-27 14:54         ` zhangfei [this message]
2015-10-27 15:03           ` Mark Rutland
     [not found]           ` <562F9016.50807-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2015-10-27 15:06             ` John Garry
     [not found]   ` <1445868903-183817-3-git-send-email-john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2015-10-26 14:55     ` John Garry
2015-10-26 14:14 ` [PATCH v2 03/32] scsi: hisi_sas: add initial bare main driver John Garry
2015-10-26 14:14 ` [PATCH v2 04/32] scsi: hisi_sas: add scsi host registration John Garry
2015-10-26 14:14 ` [PATCH v2 06/32] scsi: hisi_sas: add HW DMA structures John Garry
2015-10-26 14:14 ` [PATCH v2 07/32] scsi: hisi_sas: allocate memories and create pools John Garry
2015-10-26 14:14 ` [PATCH v2 08/32] scsi: hisi_sas: add hisi_sas_remove John Garry
2015-10-26 14:14 ` [PATCH v2 09/32] scsi: hisi_sas: add slot init code John Garry
2015-10-26 14:14 ` [PATCH v2 10/32] scsi: hisi_sas: add cq structure initialization John Garry
2015-10-26 14:14 ` [PATCH v2 11/32] scsi: hisi_sas: add phy SAS ADDR initialization John Garry
2015-10-26 14:14 ` [PATCH v2 12/32] scsi: hisi_sas: set dev DMA mask John Garry
2015-10-26 14:14 ` [PATCH v2 13/32] scsi: hisi_sas: add hisi_hba workqueue John Garry
2015-10-26 14:14 ` [PATCH v2 14/32] scsi: hisi_sas: add hisi sas device type John Garry
2015-10-26 14:14 ` [PATCH v2 15/32] scsi: hisi_sas: add phy and port init John Garry
2015-10-26 14:14 ` [PATCH v2 16/32] scsi: hisi_sas: add timer and spinlock init John Garry
2015-10-26 14:14 ` [PATCH v2 17/32] scsi: hisi_sas: add v1 hw module init John Garry
2015-10-26 14:14 ` [PATCH v2 18/32] scsi: hisi_sas: add v1 hardware register definitions John Garry
     [not found] ` <1445868903-183817-1-git-send-email-john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2015-10-26 14:14   ` [PATCH v2 05/32] scsi: hisi_sas: scan device tree John Garry
     [not found]     ` <1445868903-183817-6-git-send-email-john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2015-10-26 14:48       ` Mark Rutland
2015-10-26 14:51         ` John Garry
2015-10-26 19:55       ` kbuild test robot
2015-10-26 14:14   ` [PATCH v2 19/32] scsi: hisi_sas: add v1 HW initialisation code John Garry
2015-10-26 14:14 ` [PATCH v2 20/32] scsi: hisi_sas: add v1 hw interrupt init John Garry
2015-10-26 14:14 ` [PATCH v2 21/32] scsi: hisi_sas: add path from phyup irq to SAS framework John Garry
2015-10-26 14:14 ` [PATCH v2 22/32] scsi: hisi_sas: add ssp command function John Garry
2015-10-26 14:14 ` [PATCH v2 23/32] scsi: hisi_sas: add cq interrupt handler John Garry
2015-10-26 14:14 ` [PATCH v2 24/32] scsi: hisi_sas: add dev_found and port_formed John Garry
2015-10-26 14:14 ` [PATCH v2 25/32] scsi: hisi_sas: add abnormal irq handler John Garry
     [not found]   ` <1445868903-183817-26-git-send-email-john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2015-10-30 14:10     ` Arnd Bergmann
2015-10-30 16:58       ` John Garry
2015-10-26 14:14 ` [PATCH v2 26/32] scsi: hisi_sas: add bcast interrupt handler John Garry
2015-10-26 14:14 ` [PATCH v2 27/32] scsi: hisi_sas: add smp protocol support John Garry
     [not found]   ` <1445868903-183817-28-git-send-email-john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2015-10-30 13:53     ` Arnd Bergmann
2015-10-30 16:22       ` John Garry
2015-11-02 17:03         ` John Garry
2015-11-02 20:29           ` Arnd Bergmann
2015-11-03 11:42             ` John Garry
     [not found]               ` <56389DA6.6070103-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2015-11-03 12:27                 ` Arnd Bergmann
2015-10-26 14:14 ` [PATCH v2 28/32] scsi: hisi_sas: add scan finished and start John Garry
2015-10-26 14:15 ` [PATCH v2 29/32] scsi: hisi_sas: add tmf methods John Garry
2015-10-26 14:15 ` [PATCH v2 30/32] scsi: hisi_sas: add control phy handler John Garry
2015-10-26 14:15 ` [PATCH v2 31/32] scsi: hisi_sas: add fatal irq handler John Garry
2015-10-26 14:15 ` [PATCH v2 32/32] MAINTAINERS: add maintainer for HiSi SAS driver John Garry

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