From mboxrd@z Thu Jan 1 00:00:00 1970 From: David Milburn Subject: Re: Regarding AHCI_MAX_SG and (ATA_HORKAGE_MAX_SEC_1024) Date: Wed, 10 Aug 2016 14:38:08 -0500 Message-ID: <57AB82A0.5080104@redhat.com> References: <20160810032613.GA25053@mtj.duckdns.org> <20160810151447.GI25053@mtj.duckdns.org> <57AB4B43.2010705@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Tom Yan Cc: Tejun Heo , linux-ide@vger.kernel.org, linux-scsi@vger.kernel.org, linux-block@vger.kernel.org, LKML List-Id: linux-scsi@vger.kernel.org On 08/10/2016 12:19 PM, Tom Yan wrote: > On 10 August 2016 at 15:41, David Milburn wrote: >> Hi, >> >> The 168 makes AHCI_CMD_TBL_SZ equal to 2816 >> >> AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16) >> AHCI_CMD_TBL_SZ = 128 + (168 * 16) >> >> I think if you add in AHCI_CMD_SLOT_SZ (1024) and AHCI_RX_FIS_SZ (256) >> the DMA is 4K aligned, I think that is where the 168 came from. > > Looks like the right guess. Though AHCI_PORT_PRIV_DMA_SZ is not: > > AHCI_CMD_SLOT_SZ (1024) + AHCI_CMD_TBL_SZ (2816) + AHCI_RX_FIS_SZ (256) = 4096 > > but: > > AHCI_CMD_SLOT_SZ (1024) + AHCI_CMD_TBL_AR_SZ (2816 * 32 = 90112) + > AHCI_RX_FIS_SZ (256) = 91392 > > and AHCI_PORT_PRIV_FBS_DMA_SZ is: > > AHCI_CMD_SLOT_SZ (1024) + AHCI_CMD_TBL_AR_SZ (2816 * 32 = 90112) + > AHCI_RX_FIS_SZ * 16 (4096) = 95232 > Yes, but in both cases mem_dma gets adjusted for AHCI_CMD_SLOT_SZ (1024) and rx_fis_sz (256 or 4096 in fbs case). Thanks, David