From: Kashyap Desai <kashyap.desai@broadcom.com>
To: Tomas Henzl <thenzl@redhat.com>, Hannes Reinecke <hare@suse.de>,
"Martin K. Petersen" <martin.petersen@oracle.com>
Cc: Christoph Hellwig <hch@lst.de>,
James Bottomley <james.bottomley@hansenpartnership.com>,
Sumit Saxena <sumit.saxena@broadcom.com>,
linux-scsi@vger.kernel.org, Hannes Reinecke <hare@suse.com>
Subject: RE: [PATCH 5/5] megaraid_sas: add mmio barrier after register writes
Date: Fri, 18 Nov 2016 22:18:47 +0530 [thread overview]
Message-ID: <67e94cdd16a9f55f3a73a12a13330ed0@mail.gmail.com> (raw)
In-Reply-To: <5f6fcc3e-a48f-7909-c409-1d265ea9135c@redhat.com>
> -----Original Message-----
> From: linux-scsi-owner@vger.kernel.org [mailto:linux-scsi-
> owner@vger.kernel.org] On Behalf Of Tomas Henzl
> Sent: Friday, November 18, 2016 9:23 PM
> To: Hannes Reinecke; Martin K. Petersen
> Cc: Christoph Hellwig; James Bottomley; Sumit Saxena; linux-
> scsi@vger.kernel.org; Hannes Reinecke
> Subject: Re: [PATCH 5/5] megaraid_sas: add mmio barrier after register
writes
>
> On 11.11.2016 10:44, Hannes Reinecke wrote:
> > The megaraid_sas HBA only has a single register for I/O submission,
> > which will be hit pretty hard with scsi-mq. To ensure that the PCI
> > writes have made it across we need to add a mmio barrier after each
> > write; otherwise I've been seeing spurious command completions and I/O
> > stalls.
>
> Why is it needed that the PCI write reaches the hw exactly at this
point?
> Is it possible that this is a hw deficiency like that the hw can't
handle
> communication without tiny pauses, and so possible to remove in next
> generation?
> Thanks,
> Tomas
I think this is good to have mmiowb as we are already doing for writel()
version of megasas_return_cmd_fusion.
May be not for x86, but for some other CPU arch it is useful. I think it
become more evident while scs-mq support for more than one submission
queue patch of Hannes expose this issue.
Probably this patch is good. Intermediate PCI device (PCI bridge ?) may
cache PCI packet and eventually out of order PCI packet to MegaRAID HBA
can cause this type of spurious completion.
>
> >
> > Signed-off-by: Hannes Reinecke <hare@suse.com>
> > ---
> > drivers/scsi/megaraid/megaraid_sas_fusion.c | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/scsi/megaraid/megaraid_sas_fusion.c
> > b/drivers/scsi/megaraid/megaraid_sas_fusion.c
> > index aba53c0..729a654 100644
> > --- a/drivers/scsi/megaraid/megaraid_sas_fusion.c
> > +++ b/drivers/scsi/megaraid/megaraid_sas_fusion.c
> > @@ -196,6 +196,7 @@ inline void megasas_return_cmd_fusion(struct
> megasas_instance *instance,
> > le32_to_cpu(req_desc->u.low));
> >
> > writeq(req_data, &instance->reg_set->inbound_low_queue_port);
> > + mmiowb();
> > #else
> > unsigned long flags;
> >
>
>
> --
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next prev parent reply other threads:[~2016-11-18 16:48 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-11 9:44 [PATCH 0/5] megaraid_sas: scsi-mq support Hannes Reinecke
2016-11-11 9:44 ` [PATCH 1/5] megaraid_sas: switch to pci_alloc_irq_vectors Hannes Reinecke
2016-11-11 11:32 ` Sumit Saxena
2016-11-11 14:59 ` Hannes Reinecke
2016-11-14 12:33 ` Christoph Hellwig
2016-11-14 12:48 ` Christoph Hellwig
2016-11-11 9:44 ` [PATCH 2/5] megaraid_sas: avoid calling megasas_lookup_instance() Hannes Reinecke
2016-11-11 10:46 ` Sumit Saxena
2016-11-11 9:44 ` [PATCH 3/5] megaraid_sas: do not crash on invalid completion Hannes Reinecke
2016-11-11 11:51 ` Sumit Saxena
2016-11-11 15:07 ` Hannes Reinecke
2016-11-11 9:44 ` [PATCH 4/5] megaraid_sas: scsi-mq support Hannes Reinecke
2016-11-11 11:26 ` kbuild test robot
2016-11-11 11:56 ` Sumit Saxena
2016-11-14 11:07 ` Kashyap Desai
2016-11-11 9:44 ` [PATCH 5/5] megaraid_sas: add mmio barrier after register writes Hannes Reinecke
2016-11-11 10:47 ` Sumit Saxena
2016-11-18 15:53 ` Tomas Henzl
2016-11-18 16:48 ` Kashyap Desai [this message]
2016-11-21 15:57 ` Tomas Henzl
2016-11-30 6:14 ` Kashyap Desai
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