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Fri, 09 Oct 2026 03:20:46 -0700 (PDT) X-Received: by 2002:a17:90b:1847:b0:3a4:f6b0:7de with SMTP id 98e67ed59e1d1-3ab3a90e800mr1364937a91.22.1791541246091; Fri, 09 Oct 2026 03:20:46 -0700 (PDT) Received: from [10.217.216.105] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3ab3966dc7dsm1366459a91.2.2026.10.09.03.20.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Oct 2026 03:20:44 -0700 (PDT) Message-ID: <7416dc0a-7b4b-4d26-95bb-7f24e54dd6fe@oss.qualcomm.com> Date: Fri, 9 Oct 2026 15:50:35 +0530 Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 5/5] phy: qcom-qmp-ufs: Add Glymur support To: Dmitry Baryshkov Cc: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Avri Altman , Bart Van Assche , Bjorn Andersson , Konrad Dybcio , gopikrishna.garmidi@oss.qualcomm.com, jagadeesh.kona@oss.qualcomm.com, Abel Vesa , Abel Vesa , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, nitin.rawat@oss.qualcomm.com, sibi.sankar@oss.qualcomm.com, Taniya Das , Konrad Dybcio References: <20261007-glymur_ufs_qcb_enablement-v3-0-84cf4f861415@oss.qualcomm.com> <20261007-glymur_ufs_qcb_enablement-v3-5-84cf4f861415@oss.qualcomm.com> <7e8ea792-2336-4252-beed-7345815b0b90@oss.qualcomm.com> Content-Language: en-US From: Pradeep Pragallapati In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=BfpNQbt2 c=1 sm=1 tr=0 ts=6ac8bfff cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=_d3xwxgixdHQDNbgaEMA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-ORIG-GUID: EqKPapPNMiElwJb022GAW-TuHwgJNwju X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDA5MDA0MSBTYWx0ZWRfX0Oq4L0i5bXL9 4UKh5OZhg1xZ0nvl+SlgSoVmtStpMXcO6uY65x4nE2o4YB6CfJ3NZWOH7DX9FIN/QfechS58FCu SbVFkQVKXWIxbjbzXAygQ2LKdYs4DVIGAkVW7mYPM6vV0EiC9wQXn7SAeEL5n3XUaNKgun2cKh1 nMCrrQjHjC+Rr6DF5Sr1ixX7eTTu3VUzUCkaFajNDkJrxCpkpMhf1io3Iy3SaC5x7aWhlfL50qn M9gSFCxQUx1XHvsjag/nz1qC/yer3JsKSJueV1lznCYS0885uXAV06nnKrwcVXF3uejLIPwFJKb nW+l09JGtLKc5D0KgUPMDfo6XDIGlVB4MZ15aT/rbsTbvsJpkY+v0wY3WS9eUUbWjjrq0VhqYUq /5wMay7TIqqlB5jbVCawHdPhx1puni8m7ByIUoKS7YBFeKRyNfKt3aF6qj7tFGX+PaP0l6dR5Xj qDoW1pCnc6strR4BedA== X-Proofpoint-GUID: EqKPapPNMiElwJb022GAW-TuHwgJNwju X-Proofpoint-Spam-Info: AW1haW4tMjYxMDA5MDA0MSBTYWx0ZWRfX7xD3C2QusTA9 dydFza/RNsBQfSJcn6n0mhvI+E2H5PJ5sSbUI1rdEDUcrzL8+g3QFx7puAcZRZHyTVJP1YdUiUo Oh0HqqMkNIe4HUh4VlA9v+oDMxd48AI= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-09_03,2026-10-08_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 impostorscore=0 phishscore=0 lowpriorityscore=0 spamscore=0 bulkscore=0 adultscore=0 clxscore=1015 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610020000 definitions=main-2610090041 On 10/7/2026 9:17 PM, Dmitry Baryshkov wrote: > On Wed, Oct 07, 2026 at 08:15:39PM +0530, Pradeep Pragallapati wrote: >> >> >> On 10/7/2026 7:13 PM, Dmitry Baryshkov wrote: >>> On Wed, Oct 07, 2026 at 05:03:02PM +0530, Pradeep Pragallapati wrote: >>>> >>>> >>>> On 10/7/2026 1:18 PM, Dmitry Baryshkov wrote: >>>>> On Wed, Oct 07, 2026 at 11:59:38AM +0530, Pradeep P V K wrote: >>>>>> Add the init sequence tables and config for the UFS QMP phy found in >>>>>> the Glymur SoC. >>>>>> >>>>>> Reviewed-by: Abel Vesa >>>>>> Acked-by: Konrad Dybcio >>>>>> Signed-off-by: Pradeep P V K >>>>>> --- >>>>>> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 99 +++++++++++++++++++++++++++++++++ >>>>>> 1 file changed, 99 insertions(+) >>>>>> >>>>>> + .offsets = &qmp_ufs_offsets_v6, >>>>> >>>>> So, is it a PHY using v6 offsets, but v7 registers inside? >>>>> >>>> The QSERDES RX0 register offsets on Glymur SoC are aligned with the v7 register layout offsets. >>>> Therefore, the v7 QSERDES RX0 register offsets are used for Glymur (similar to SM8750). >>> >>> Mention in the commit message, please. >> sure, i will mention it.> >>>> >>>>>> + .max_supported_gear = UFS_HS_G5, >>>>>> + >>>>>> + .vreg_list = glymur_ufsphy_vreg_l, >>>>>> + .num_vregs = ARRAY_SIZE(glymur_ufsphy_vreg_l), >>>>>> + .regs = ufsphy_v6_regs_layout, >>>>> >>>>> v7 >>> >>> This still holds. >>> >> Do you mean changing ufsphy_v6_regs_layout to ufsphy_v7_regs_layout? >> If so, no. ufsphy_v6_regs_layout contains the PCS register offsets, and the >> PCS register offsets on Glymur are aligned with ufsphy_v6_regs_layout, similar to SM8750. > > => commit message, please. > sure, i will update the commit message in my next patch series.