From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Nitin Rawat <nitin.rawat@oss.qualcomm.com>,
mani@kernel.org, James.Bottomley@HansenPartnership.com,
martin.petersen@oracle.com
Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-scsi@vger.kernel.org
Subject: Re: [PATCH V1 2/3] ufs: ufs-qcom: Align programming sequence for UFS controller v6.2
Date: Thu, 22 Jan 2026 16:09:40 +0100 [thread overview]
Message-ID: <883a2f40-a945-47f0-8022-20ad4146acf3@oss.qualcomm.com> (raw)
In-Reply-To: <20260122141331.239354-3-nitin.rawat@oss.qualcomm.com>
On 1/22/26 3:13 PM, Nitin Rawat wrote:
> UFS controller v6.2 requires bit 31 in the spare configuration register
> to be set for high-speed link startup mode, as per the Hardware
> Programming Guide (HPG).
Please stick a "Qualcomm" before mentioning UFS controller v6.2, I
don't think that is immediately obvious without looking at the code..
> The spare register value is read during host driver initialization but
> gets cleared after UFS reset. To align with the UFS v6.2 programming
> sequence, preserve the spare register value during initialization and
> restore it during link startup to ensure proper high-speed mode
I believe you're supposed to write the value yourself, depending on the
state of the controller, it's 0 at reset.
> Signed-off-by: Nitin Rawat <nitin.rawat@oss.qualcomm.com>
> ---
> drivers/ufs/host/ufs-qcom.c | 11 ++++++++---
> drivers/ufs/host/ufs-qcom.h | 1 +
> 2 files changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> index c43bb75d208c..ab5aed241913 100644
> --- a/drivers/ufs/host/ufs-qcom.c
> +++ b/drivers/ufs/host/ufs-qcom.c
> @@ -686,6 +686,7 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, bool is_pre_scale_up, unsign
> static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
> enum ufs_notify_change_status status)
> {
> + struct ufs_qcom_host *host = ufshcd_get_variant(hba);
> int err = 0;
>
> switch (status) {
> @@ -708,6 +709,10 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
> */
> err = ufshcd_disable_host_tx_lcc(hba);
>
> + /* Update REG_UFS_DEBUG_SPARE_CFG to set HS-LSS mode in link startup */
"HS/LS"?
> + if (host->hw_ver.major == 0x6 && host->hw_ver.minor == 0x2)
> + ufshcd_writel(hba, host->spare_cfg,
> + REG_UFS_DEBUG_SPARE_CFG);
Is that a "only on v6.2", or "starting with v6.2"?
Also, I see that this register has more than just this one field, with
the previous question in mind, I think a rmw would be desired here
Konrad
next prev parent reply other threads:[~2026-01-22 15:09 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-22 14:13 [PATCH V1 0/3] ufs: ufs-qcom: Fixes and optimizations for Qualcomm UFS platform Nitin Rawat
2026-01-22 14:13 ` [PATCH V1 1/3] ufs: ufs-qcom: Add UFS ESI CPU affinity support Nitin Rawat
2026-01-23 0:57 ` Bart Van Assche
2026-01-22 14:13 ` [PATCH V1 2/3] ufs: ufs-qcom: Align programming sequence for UFS controller v6.2 Nitin Rawat
2026-01-22 15:09 ` Konrad Dybcio [this message]
2026-01-22 14:13 ` [PATCH V1 3/3] ufs: ufs-qcom: Fix sequential read variance Nitin Rawat
2026-01-22 15:11 ` Konrad Dybcio
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