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[73.231.117.72]) by smtp.gmail.com with ESMTPSA id 30-20020a17090a01de00b002794fe14cabsm4068946pjd.12.2023.10.27.13.55.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 27 Oct 2023 13:55:23 -0700 (PDT) Message-ID: Date: Fri, 27 Oct 2023 13:55:20 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 1/1] ufs: core: Add host quirk QUIRK_MCQ_EXPAND_QUEUE_SLOT Content-Language: en-US To: =?UTF-8?B?Q2h1bi1IdW5nIFd1ICjlt6vpp7/lro8p?= , "ebiggers@google.com" , "quic_nguyenb@quicinc.com" , "jejb@linux.ibm.com" , "avri.altman@wdc.com" , "martin.petersen@oracle.com" , "quic_asutoshd@quicinc.com" , "alim.akhtar@samsung.com" , "Arthur.Simchaev@wdc.com" , "keosung.park@samsung.com" , "mani@kernel.org" , "matthias.bgg@gmail.com" , "quic_cang@quicinc.com" , "angelogioacchino.delregno@collabora.com" , "yang.lee@linux.alibaba.com" Cc: =?UTF-8?B?UGV0ZXIgV2FuZyAo546L5L+h5Y+LKQ==?= , =?UTF-8?B?RWRkaWUgSHVhbmcgKOm7g+aZuuWCkSk=?= , =?UTF-8?B?SmlhamllIEhhbyAo6YOd5Yqg6IqCKQ==?= , =?UTF-8?B?Q0MgQ2hvdSAo5ZGo5b+X5p2wKQ==?= , "linux-kernel@vger.kernel.org" , =?UTF-8?B?QWxpY2UgQ2hhbyAo6LaZ54+u5Z2HKQ==?= , "linux-mediatek@lists.infradead.org" , wsd_upstream , =?UTF-8?B?Q2FzcGVyIExpICjmnY7kuK3mpq4p?= , =?UTF-8?B?VHVuLXl1IFl1ICjmuLjmlabogb8p?= , "linux-scsi@vger.kernel.org" , =?UTF-8?B?TGluIEd1aSAo5qGC5p6XKQ==?= , =?UTF-8?B?Q2hhb3RpYW4gSmluZyAo5LqV5pyd5aSpKQ==?= , =?UTF-8?B?UG93ZW4gS2FvICjpq5jkvK/mlocp?= , =?UTF-8?B?TmFvbWkgQ2h1ICjmnLHoqaDnlLAp?= , "linux-arm-kernel@lists.infradead.org" , =?UTF-8?B?UWlsaW4gVGFuICjosK3pupLpup8p?= , "kernel-team@android.com" References: <20231025085656.10848-1-chun-hung.wu@mediatek.com> <20231025085656.10848-2-chun-hung.wu@mediatek.com> <3056c6d8-1e54-4954-9141-e0760a0d935a@acm.org> <53d7d12bc12237e5f86522faf09876ab08ef7592.camel@mediatek.com> From: Bart Van Assche In-Reply-To: <53d7d12bc12237e5f86522faf09876ab08ef7592.camel@mediatek.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org On 10/26/23 20:27, Chun-Hung Wu (巫駿宏) wrote: > From UFSHCI 4.0 spec "When the head and tail doorbells are equal, the > queue is empty. *Nothe that this definition means there will always be > one empty queue entry" > One of our platform does not keep one empty queue > entry for CQ full > case, that's why we need this patch to fix this corner case. The UFSHCI driver should make sure that there is always one empty queue entry. Does "platform" in the above text refer to the SoC that includes the UFSHCI controller? What is totally unclear to me is why the following code depends on the UFSHCI controller type: + if (ufshcd_is_mcq_expand_queue_slot(hba)) + hwq->max_entries = hba->nutrs + 1; + else + hwq->max_entries = hba->nutrs; Shouldn't hwq->max_entries = hba->nutrs + 1 be used for all UFSHCI 4.0 controllers? Thanks, Bart.