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Fri, 17 Apr 2026 06:29:49 -0700 (PDT) X-Received: by 2002:a05:6a00:a241:b0:822:6830:5900 with SMTP id d2e1a72fcca58-82f8c7eee25mr2726388b3a.6.1776432589265; Fri, 17 Apr 2026 06:29:49 -0700 (PDT) Received: from [10.217.223.121] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82f8ea0a97esm2695706b3a.27.2026.04.17.06.29.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 17 Apr 2026 06:29:48 -0700 (PDT) Message-ID: Date: Fri, 17 Apr 2026 18:59:42 +0530 Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 3/5] mmc: sdhci-msm: Set ICE clk to TURBO at sdhci ICE init To: Abhinaba Rakshit , Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , "James E.J. Bottomley" , "Martin K. Petersen" , Adrian Hunter , Ulf Hansson , Neeraj Soni , Kuldeep Singh , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio References: <20260409-enable-ice-clock-scaling-v8-0-ca1129798606@oss.qualcomm.com> <20260409-enable-ice-clock-scaling-v8-3-ca1129798606@oss.qualcomm.com> Content-Language: en-US From: Harshal Dev In-Reply-To: <20260409-enable-ice-clock-scaling-v8-3-ca1129798606@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: ePXGlc6fZSkPp3UmYzaVcB5FYpQWh7b0 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDE3MDEzNSBTYWx0ZWRfX5b/FUZVDPHPN SuhjHttVzLTKHsw/Sjgod83jFz8MVe5ItBsPshp0tFFSYEoF5Rtf2lIrhSaI7Mx52Vol9xm4V3S 65liXkVglyhJa2qPsV6esRs9BTTzazMpqhMBCQkvuzDWulD+lZnkf03nNnUBl2urWtA1YjontfL RldWNRU9x+c6CeTtGA+rkn8Akk6/VlHNX947msrqaxMArMD8dMideSaVypgqPX2wfavIieXLIH4 6O1aIlEtxp4w6R2JwKWn1XKIVkMTK2TafBVosP497TSC8u+mpAqepFdbsl+DnSJ+/8VJ6OQZ3Pa KPA8BLkKc6flX9ANKuK4osVFIqi0RiEJLJ/ZgeOsKMUKISEoufnvNw/HeGpLSflSiZT42o8BHoR R10q4XVgNCXdF4fOYpFH058TDL9A7i3ygWWoVhGy1awXN7c9YioPHA3sK+MmuK3J2FBhOCqYnAh 58UO5kKUl5VR9gql/Tw== X-Authority-Analysis: v=2.4 cv=GN041ONK c=1 sm=1 tr=0 ts=69e235ce cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=i-sMpDq2_rzAXM5hadQA:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-GUID: ePXGlc6fZSkPp3UmYzaVcB5FYpQWh7b0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-17_01,2026-04-17_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 spamscore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 bulkscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604170135 On 4/9/2026 5:14 PM, Abhinaba Rakshit wrote: > MMC controller lacks a clock scaling mechanism, unlike the UFS > controller. By default, the MMC controller is set to TURBO mode > during probe, but the ICE clock remains at XO frequency, > leading to read/write performance degradation on eMMC. > > To address this, set the ICE clock to TURBO during sdhci_msm_ice_init > to align it with the controller clock. This ensures consistent > performance and avoids mismatches between the controller > and ICE clock frequencies. > > For platforms where ICE is represented as a separate device, > use the OPP framework to vote for TURBO mode, maintaining > proper voltage and power domain constraints. > > Reviewed-by: Konrad Dybcio > Signed-off-by: Abhinaba Rakshit > --- > drivers/mmc/host/sdhci-msm.c | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > [...] > > static const struct blk_crypto_ll_ops sdhci_msm_crypto_ops; /* forward decl */ > +static int sdhci_msm_ice_scale_clk(struct sdhci_msm_host *msm_host, unsigned long target_freq, > + bool round_ceil); /* forward decl */ > > static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host, > struct cqhci_host *cq_host) > @@ -1964,6 +1966,11 @@ static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host, > } > > mmc->caps2 |= MMC_CAP2_CRYPTO; > + > + err = sdhci_msm_ice_scale_clk(msm_host, INT_MAX, false); The 2nd parameter is an unsigned long, do you really want to pass INT_MAX here? I would go with UINT_MAX. But still, why go with such a high value? Do we not have an upper bound for the clk frequency that we know we can't ever exceed for any target across OPP tables? If not, then maybe UINT_MAX is best we can do here. Regards, Harshal > + if (err && err != -EOPNOTSUPP) > + dev_warn(dev, "Unable to boost ICE clock to TURBO\n"); > + > return 0; > } > > @@ -1989,6 +1996,16 @@ static int sdhci_msm_ice_suspend(struct sdhci_msm_host *msm_host) > return 0; > } > > +static int sdhci_msm_ice_scale_clk(struct sdhci_msm_host *msm_host, > + unsigned long target_freq, > + bool round_ceil) > +{ > + if (msm_host->mmc->caps2 & MMC_CAP2_CRYPTO) > + return qcom_ice_scale_clk(msm_host->ice, target_freq, round_ceil); > + > + return 0; > +} > +