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Mon, 22 Jun 2026 00:35:05 -0700 (PDT) Received: from hu-arakshit-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84564d8dddbsm6607972b3a.19.2026.06.22.00.35.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jun 2026 00:35:05 -0700 (PDT) Date: Mon, 22 Jun 2026 13:04:58 +0530 From: Abhinaba Rakshit To: Konrad Dybcio Cc: Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , "James E.J. Bottomley" , "Martin K. Petersen" , Adrian Hunter , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neeraj Soni , Harshal Dev , Kuldeep Singh , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v11 1/6] soc: qcom: ice: Add OPP-based clock scaling support for ICE Message-ID: References: <20260609-enable-ice-clock-scaling-v11-0-1cebc8b3275b@oss.qualcomm.com> <20260609-enable-ice-clock-scaling-v11-1-1cebc8b3275b@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjIyMDA3MyBTYWx0ZWRfXzbOLW2Krpya0 JOEZLAc+Lnn3XUrxmtwjgs3sweXw3YvGbA2H+IpDIbFsqr0n7U7I6YKn4D+YOTq2kjn8Tn8WxU1 95w2uFR+YaoXRRaF81EJ6zubg0XIEVQ+Qo3rIKaxZxK5idtbDhLNJuvazfsOqrhoDQdI9taTdRp 1T3+nD4Bom3hLe+H3rynTAbvlqj2tCD6Hq9uFBv2S2g1u8l42ywMYwgVlP+dXz7YstgkTSjcp46 cWwaDBfwgriFd0QVX7hCvcEns6zVy/6g5rgYC6EfBWgzKgF4EMFQ4QhVC1HDmbrxEtF1ShgjDC5 UzKBt+N2sboMmOeGrjESEXhIUPqMF8jZoZZPwiM1kI2X03kU1kecMGp1Wh9OtPQzt4Zk5S2vG+G iLt5doXCLDpqr0MkQCsF1ZpS0nOqVQRkfW+jU8a58WhvSSLwsWH50RN33WanldVdl+P56ZUL8GQ hPIAfDDtBnPjvHkYvOg== X-Proofpoint-Spam-Info: AW1haW4tMjYwNjIyMDA3MyBTYWx0ZWRfX11fOB6bua+6Q uDv5IgjPMEp46e4aN4ec51JSrbYm69/WTo1bnwEVuITVN4F1Pw8LYWCEgbEKiuheWVz6xHX27/b zBkYrGmnFoeIHZsTcUWVYqWLD959iiA= X-Proofpoint-ORIG-GUID: Go8bJ5lPmtyzOPsv_Pwwj373c63sEJGg X-Proofpoint-GUID: Go8bJ5lPmtyzOPsv_Pwwj373c63sEJGg X-Authority-Analysis: v=2.4 cv=UrZT8ewB c=1 sm=1 tr=0 ts=6a38e5ab cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=kj9zAlcOel0A:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=cYz2LKHLP3dAwZc2OesA:9 a=CjuIK1q_8ugA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-22_01,2026-06-18_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 phishscore=0 impostorscore=0 clxscore=1015 malwarescore=0 bulkscore=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606220073 On Thu, Jun 18, 2026 at 03:01:54PM +0200, Konrad Dybcio wrote: > On 6/8/26 11:47 PM, Abhinaba Rakshit wrote: > > Register optional operation-points-v2 table for ICE device > > during device probe. Attach the OPP-table with only the ICE > > core clock. Since, dtbinding is on a transition phase to include > > iface clock and clock-names, attaching the opp-table to core clock > > remains optional such that it does not cause probe failures. > > > > Introduce clock scaling API qcom_ice_scale_clk which scale ICE > > core clock based on the target frequency provided and if a valid > > OPP-table is registered. Use round_ceil passed to decide on the > > rounding of the clock freq against OPP-table. Clock scaling is > > disabled when a valid OPP-table is not registered. > > > > This ensures when an ICE-device specific OPP table is available, > > use the PM OPP framework to manage frequency scaling and maintain > > proper power-domain constraints. > > > > Also, ensure to drop the votes in suspend to prevent power/thermal > > retention. Subsequently restore the frequency in resume from > > core_clk_freq which stores the last ICE core clock operating frequency. > > > > Reviewed-by: Harshal Dev > > Signed-off-by: Abhinaba Rakshit > > --- > > [...] > > > @@ -335,6 +342,11 @@ int qcom_ice_suspend(struct qcom_ice *ice) > > { > > clk_disable_unprepare(ice->iface_clk); > > clk_disable_unprepare(ice->core_clk); > > + > > + /* Drop the clock votes while suspend */ > > + if (ice->has_opp) > > + dev_pm_opp_set_rate(ice->dev, 0); > > The PM core will quiesce the vote as the device suspends, this is > unnecessary. Similarly, the rate restore logic will become unnecessary. > Especially since dev_pm_opp_set_rate(0) does not actually do any rate > setting. This section was earlier discussed in the patchset v4: https://lore.kernel.org/all/7b219a50-6971-4a0c-a465-418f8abd5556@oss.qualcomm.com/ The intention here was to drop the RPMh votes once the device goes to suspend same as the storage drivers such as mmc drivers does: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/mmc/host/sdhci-msm.c#n2946 This was done to leave the hanging votes *on* for unused clocks. However, I get your point, due to mean to say that once device goes to suspend and GDSC power-domain will be turned OFF, it will automatically quiesce the performance votes? Abhinaba Rakshit