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From: Frank Li <Frank.li@oss.nxp.com>
To: Larisa Grigore <larisa.grigore@oss.nxp.com>
Cc: NXP S32 Linux Team <s32@nxp.com>,
	Alim Akhtar <alim.akhtar@samsung.com>,
	Avri Altman <avri.altman@sandisk.com>,
	Bart Van Assche <bvanassche@acm.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>, Frank Li <Frank.Li@nxp.com>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	Pengutronix Kernel Team <kernel@pengutronix.de>,
	Fabio Estevam <festevam@gmail.com>,
	"James E . J . Bottomley" <James.Bottomley@hansenpartnership.com>,
	"Martin K . Petersen" <martin.petersen@oracle.com>,
	Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>,
	Ajay Neeli <ajay.neeli@amd.com>,
	Manivannan Sadhasivam <mani@kernel.org>,
	Pedro Sousa <pedrom.sousa@synopsys.com>,
	clizzi@redhat.com, aruizrui@redhat.com, eballetb@redhat.com,
	echanude@redhat.com, linux-scsi@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
	linux-arm-msm@vger.kernel.org
Subject: Re: [PATCH 02/10] ufs: unipro: Add TX/RX FSM state attributes
Date: Wed, 26 Aug 2026 10:09:01 -0500	[thread overview]
Message-ID: <ao8BjTPouw7t7xfs@SMW015318> (raw)
In-Reply-To: <20260826134048.854748-3-larisa.grigore@oss.nxp.com>

On Wed, Aug 26, 2026 at 03:40:40PM +0200, Larisa Grigore wrote:
>
> Add TX_FSM_STATE and RX_FSM_STATE to include/ufs/unipro.h, as these are
> UniPro M-PHY attribute definitions rather than host controller specific
> ones.
>
> Remove the duplicated local definitions from the HiSilicon, Qualcomm, AMD
> Versal and DesignWare UFS headers.
>
> This also prepares for using these definitions in a subsequent commit.
>
> Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com>
> ---

Nice cleanup,

Reviewed-by: Frank Li <Frank.Li@nxp.com>


>  drivers/ufs/host/ufs-amd-versal2.c | 4 ++--
>  drivers/ufs/host/ufs-hisi.c        | 8 ++++----
>  drivers/ufs/host/ufs-hisi.h        | 5 -----
>  drivers/ufs/host/ufs-qcom.c        | 4 ++--
>  drivers/ufs/host/ufs-qcom.h        | 1 -
>  drivers/ufs/host/ufshcd-dwc.h      | 4 ----
>  include/ufs/unipro.h               | 2 ++
>  7 files changed, 10 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/ufs/host/ufs-amd-versal2.c b/drivers/ufs/host/ufs-amd-versal2.c
> index 2154d6286817..0d4d5e98ad65 100644
> --- a/drivers/ufs/host/ufs-amd-versal2.c
> +++ b/drivers/ufs/host/ufs-amd-versal2.c
> @@ -112,7 +112,7 @@ static int ufs_versal2_enable_phy(struct ufs_hba *hba)
>                 u32 time_left, mibsel;
>
>                 time_left = TIMEOUT_MICROSEC;
> -               mibsel = UIC_ARG_MIB_SEL(MTX_FSM_STATE, UIC_ARG_MPHY_TX_GEN_SEL_INDEX(offset));
> +               mibsel = UIC_ARG_MIB_SEL(TX_FSM_STATE, UIC_ARG_MPHY_TX_GEN_SEL_INDEX(offset));
>                 do {
>                         ret = ufshcd_dme_get(hba, mibsel, &reg);
>                         if (ret)
> @@ -132,7 +132,7 @@ static int ufs_versal2_enable_phy(struct ufs_hba *hba)
>                 }
>
>                 time_left = TIMEOUT_MICROSEC;
> -               mibsel = UIC_ARG_MIB_SEL(MRX_FSM_STATE, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(offset));
> +               mibsel = UIC_ARG_MIB_SEL(RX_FSM_STATE, UIC_ARG_MPHY_RX_GEN_SEL_INDEX(offset));
>                 do {
>                         ret = ufshcd_dme_get(hba, mibsel, &reg);
>                         if (ret)
> diff --git a/drivers/ufs/host/ufs-hisi.c b/drivers/ufs/host/ufs-hisi.c
> index 2d214ce9620e..bd223bda1ce2 100644
> --- a/drivers/ufs/host/ufs-hisi.c
> +++ b/drivers/ufs/host/ufs-hisi.c
> @@ -30,10 +30,10 @@ static int ufs_hisi_check_hibern8(struct ufs_hba *hba)
>         unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
>
>         do {
> -               err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 0),
> +               err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(TX_FSM_STATE, 0),
>                                       &tx_fsm_val_0);
>                 err |= ufshcd_dme_get(hba,
> -                   UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 1), &tx_fsm_val_1);
> +                   UIC_ARG_MIB_SEL(TX_FSM_STATE, 1), &tx_fsm_val_1);
>                 if (err || (tx_fsm_val_0 == TX_STATE_HIBERN8 &&
>                         tx_fsm_val_1 == TX_STATE_HIBERN8))
>                         break;
> @@ -47,10 +47,10 @@ static int ufs_hisi_check_hibern8(struct ufs_hba *hba)
>          * check the state again.
>          */
>         if (time_after(jiffies, timeout)) {
> -               err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 0),
> +               err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(TX_FSM_STATE, 0),
>                                      &tx_fsm_val_0);
>                 err |= ufshcd_dme_get(hba,
> -                UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 1), &tx_fsm_val_1);
> +                UIC_ARG_MIB_SEL(TX_FSM_STATE, 1), &tx_fsm_val_1);
>         }
>
>         if (err) {
> diff --git a/drivers/ufs/host/ufs-hisi.h b/drivers/ufs/host/ufs-hisi.h
> index 6af6a268458d..08dccfbec404 100644
> --- a/drivers/ufs/host/ufs-hisi.h
> +++ b/drivers/ufs/host/ufs-hisi.h
> @@ -39,11 +39,6 @@
>  #define MASK_UFS_DEVICE_RESET          (0x1 << 16)
>  #define BIT_UFS_DEVICE_RESET           (0x1)
>
> -/*
> - * M-TX Configuration Attributes for Hixxxx
> - */
> -#define MPHY_TX_FSM_STATE      0x41
> -
>  /*
>   * Hixxxx UFS HC specific Registers
>   */
> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> index 75f569dd5cfe..b2081ed6197a 100644
> --- a/drivers/ufs/host/ufs-qcom.c
> +++ b/drivers/ufs/host/ufs-qcom.c
> @@ -390,7 +390,7 @@ static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
>
>         do {
>                 err = ufshcd_dme_get(hba,
> -                               UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
> +                               UIC_ARG_MIB_SEL(TX_FSM_STATE,
>                                         UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
>                                 &tx_fsm_val);
>                 if (err || tx_fsm_val == TX_STATE_HIBERN8)
> @@ -406,7 +406,7 @@ static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
>          */
>         if (time_after(jiffies, timeout))
>                 err = ufshcd_dme_get(hba,
> -                               UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
> +                               UIC_ARG_MIB_SEL(TX_FSM_STATE,
>                                         UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
>                                 &tx_fsm_val);
>
> diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
> index b7b68333fc32..fc24ed995ff3 100644
> --- a/drivers/ufs/host/ufs-qcom.h
> +++ b/drivers/ufs/host/ufs-qcom.h
> @@ -10,7 +10,6 @@
>  #include <soc/qcom/ice.h>
>  #include <ufs/ufshcd.h>
>
> -#define MPHY_TX_FSM_STATE       0x41
>  #define HBRN8_POLL_TOUT_MS      100
>  #define DEFAULT_CLK_RATE_HZ     1000000
>  #define MAX_SUPP_MAC           64
> diff --git a/drivers/ufs/host/ufshcd-dwc.h b/drivers/ufs/host/ufshcd-dwc.h
> index a5e40e7604a1..0406f2bb576b 100644
> --- a/drivers/ufs/host/ufshcd-dwc.h
> +++ b/drivers/ufs/host/ufshcd-dwc.h
> @@ -27,10 +27,6 @@
>
>  #define CBREFREFCLK_GATE_OVR_EN                BIT(7)
>
> -/* M-PHY Attributes */
> -#define MTX_FSM_STATE          0x41
> -#define MRX_FSM_STATE          0xC1
> -
>  /* M-PHY registers */
>  #define RX_OVRD_IN_1(n)                (0x3006 + ((n) * 0x100))
>  #define RX_PCS_OUT(n)          (0x300F + ((n) * 0x100))
> diff --git a/include/ufs/unipro.h b/include/ufs/unipro.h
> index bf063edc284d..d9fcdf922482 100644
> --- a/include/ufs/unipro.h
> +++ b/include/ufs/unipro.h
> @@ -34,6 +34,7 @@
>  #define TX_PWM_G6_G7_SYNC_LENGTH               0x0034
>  #define TX_HS_DEEMPHASIS_SETTING               0x0037
>  #define TX_HS_PRESHOOT_SETTING                 0x003B
> +#define TX_FSM_STATE                           0x0041
>  #define TX_REFCLKFREQ                          0x00EB
>  #define TX_CFGCLKFREQVAL                       0x00EC
>  #define        CFGEXTRATTR                             0x00F0
> @@ -72,6 +73,7 @@
>  #define CFGRXCDR8                              0x00BA
>  #define CFGRXOVR8                              0x00BD
>  #define CFGRXOVR6                              0x00BF
> +#define RX_FSM_STATE                           0x00C1
>  #define RX_FOM                                 0x00C2
>  #define RXDIRECTCTRL2                          0x00C7
>  #define CFGRXOVR4                              0x00E9
> --
> 2.43.0
>
>

  reply	other threads:[~2026-08-26 15:09 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-26 13:40 [PATCH 00/10] Add S32N79RDB UFS support Larisa Grigore
2026-08-26 13:40 ` [PATCH 01/10] ufs: unipro: Move Tx/Rx FSM state definitions to unipro.h Larisa Grigore
2026-08-26 15:05   ` Frank Li
2026-08-27 13:59     ` Larisa Ileana Grigore
2026-08-27 15:11       ` Bart Van Assche
2026-08-26 13:40 ` [PATCH 02/10] ufs: unipro: Add TX/RX FSM state attributes Larisa Grigore
2026-08-26 15:09   ` Frank Li [this message]
2026-08-26 13:40 ` [PATCH 03/10] ufs: host: Add common Hibern8 TX FSM polling helper Larisa Grigore
2026-08-26 15:17   ` Frank Li
2026-08-26 15:33   ` Bart Van Assche
2026-08-27 14:03     ` Larisa Ileana Grigore
2026-08-27  9:14   ` Bough Chen
2026-08-27 14:10     ` Larisa Ileana Grigore
2026-08-27 15:00   ` Stanley Jhu
2026-08-26 13:40 ` [PATCH 04/10] scsi: ufs: Move Versal2 M-PHY CREG access helpers into ufshcd-dwc Larisa Grigore
2026-08-26 15:20   ` Frank Li
2026-08-27 14:11     ` Larisa Ileana Grigore
2026-08-26 15:36   ` Bart Van Assche
2026-08-27 14:13     ` Larisa Ileana Grigore
2026-08-27 10:47   ` Bough Chen
2026-08-26 13:40 ` [PATCH 05/10] scsi: ufs: dwc: Export common clock divider and link status helpers Larisa Grigore
2026-08-26 15:22   ` Frank Li
2026-08-26 13:40 ` [PATCH 06/10] dt-bindings: ufs: Add compatibles for S32N79 Host Controller platform driver Larisa Grigore
2026-08-26 14:35   ` Frank Li
2026-08-26 15:57     ` Conor Dooley
2026-08-27 14:37       ` Larisa Ileana Grigore
2026-08-27 14:36     ` Larisa Ileana Grigore
2026-08-27 14:45       ` Frank Li
2026-08-27 15:09         ` Larisa Ileana Grigore
2026-08-26 13:40 ` [PATCH 07/10] scsi: ufs: Add NXP S32N79 UFS host controller driver Larisa Grigore
2026-08-26 14:01   ` sashiko-bot
2026-08-26 15:49   ` Frank Li
2026-08-27 14:44     ` Larisa Ileana Grigore
2026-08-26 13:40 ` [PATCH 08/10] arm64: dts: freescale: s32n79: Add UFS host controller Larisa Grigore
2026-08-26 13:40 ` [PATCH 09/10] arm64: dts: freescale: s32n79-rdb: Enable UFS Larisa Grigore
2026-08-26 13:40 ` [PATCH 10/10] MAINTAINERS: Add NXP S32N7 UFS host controller entry Larisa Grigore

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