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Sat, 08 Feb 2025 19:18:10 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 518JI8gX002434 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 8 Feb 2025 19:18:09 GMT Received: from [10.216.46.73] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sat, 8 Feb 2025 11:18:00 -0800 Message-ID: Date: Sun, 9 Feb 2025 00:47:56 +0530 Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/5] arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC To: Dmitry Baryshkov , Melody Olvera CC: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Alim Akhtar , Avri Altman , Bart Van Assche , Bjorn Andersson , Andy Gross , Konrad Dybcio , Satya Durga Srinivasu Prabhala , Trilok Soni , , , , , , Manish Pandey References: <20250113-sm8750_ufs_master-v1-0-b3774120eb8c@quicinc.com> <20250113-sm8750_ufs_master-v1-4-b3774120eb8c@quicinc.com> Content-Language: en-US From: Nitin Rawat In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: H7MMEz91xnntvLV_dF1Nb-28qP3oy1uj X-Proofpoint-ORIG-GUID: H7MMEz91xnntvLV_dF1Nb-28qP3oy1uj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-08_08,2025-02-07_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 impostorscore=0 malwarescore=0 priorityscore=1501 suspectscore=0 clxscore=1015 mlxscore=0 bulkscore=0 lowpriorityscore=0 adultscore=0 phishscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502080163 On 1/14/2025 4:22 PM, Dmitry Baryshkov wrote: > On Mon, Jan 13, 2025 at 01:46:27PM -0800, Melody Olvera wrote: >> From: Nitin Rawat >> >> Add UFS host controller and PHY nodes for SM8750 SoC. >> >> Co-developed-by: Manish Pandey >> Signed-off-by: Manish Pandey >> Signed-off-by: Nitin Rawat >> Signed-off-by: Melody Olvera >> --- >> arch/arm64/boot/dts/qcom/sm8750.dtsi | 81 ++++++++++++++++++++++++++++++++++++ >> 1 file changed, 81 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi >> index 3bbd7d18598ee0a3a0d5130c03a3166e1fc14d82..20690c102244b337847a6482dd83c37e19746de9 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi >> @@ -13,6 +13,7 @@ >> #include >> #include >> #include >> +#include >> >> / { >> interrupt-parent = <&intc>; >> @@ -1939,6 +1940,86 @@ mmss_noc: interconnect@1780000 { >> #interconnect-cells = <2>; >> }; >> >> + ufs_mem_phy: phy@1d80000 { >> + compatible = "qcom,sm8750-qmp-ufs-phy"; >> + reg = <0x0 0x01d80000 0x0 0x2000>; >> + >> + clocks = <&rpmhcc RPMH_CXO_CLK>, >> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, >> + <&tcsrcc TCSR_UFS_CLKREF_EN>; >> + clock-names = "ref", >> + "ref_aux", >> + "qref"; >> + >> + resets = <&ufs_mem_hc 0>; >> + reset-names = "ufsphy"; >> + >> + power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>; >> + >> + #clock-cells = <1>; >> + #phy-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + ufs_mem_hc: ufs@1d84000 { >> + compatible = "qcom,sm8750-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; >> + reg = <0x0 0x01d84000 0x0 0x3000>; >> + >> + interrupts = ; >> + >> + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, >> + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, >> + <&gcc GCC_UFS_PHY_AHB_CLK>, >> + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, >> + <&rpmhcc RPMH_LN_BB_CLK3>, >> + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, >> + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, >> + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; >> + clock-names = "core_clk", >> + "bus_aggr_clk", >> + "iface_clk", >> + "core_clk_unipro", >> + "ref_clk", >> + "tx_lane0_sync_clk", >> + "rx_lane0_sync_clk", >> + "rx_lane1_sync_clk"; >> + freq-table-hz = <100000000 403000000>, >> + <0 0>, >> + <0 0>, >> + <100000000 403000000>, >> + <100000000 403000000>, >> + <0 0>, >> + <0 0>, >> + <0 0>; > > Use OPP table instead Currently, OPP is not enabled in the device tree for any previous targets. I plan to enable OPP in a separate patch at a later stage. This is because there is an ongoing patch in the upstream that aims to enable multiple-level clock scaling using OPP, which may introduce changes to the device tree entries. To avoid extra efforts, I intend to enable OPP once that patch is merged. Please let me know if you have any concerns. > >> + >> + resets = <&gcc GCC_UFS_PHY_BCR>; >> + reset-names = "rst"; >> + >> + >> + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; > > Shouldn't cpu-ufs be ACTIVE_ONLY? As per ufs driver implementation, Icc voting from ufs driver is removed as part of low power mode (suspend or clock gating) and voted again in resume/ungating path. Hence TAG_ALWAYS will have no power concern. All previous targets have the same configuration. Thanks, Nitin > >> + interconnect-names = "ufs-ddr", >> + "cpu-ufs"; >> + >> + power-domains = <&gcc GCC_UFS_PHY_GDSC>; >> + required-opps = <&rpmhpd_opp_nom>; >> + >> + iommus = <&apps_smmu 0x60 0>; >> + dma-coherent; >> + >> + lanes-per-direction = <2>; >> + >> + phys = <&ufs_mem_phy>; >> + phy-names = "ufsphy"; >> + >> + #reset-cells = <1>; >> + >> + status = "disabled"; >> + }; >> + >> tcsr_mutex: hwlock@1f40000 { >> compatible = "qcom,tcsr-mutex"; >> reg = <0x0 0x01f40000 0x0 0x20000>; >> >> -- >> 2.46.1 >> >