From: Adrian Hunter <adrian.hunter@intel.com>
To: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"James E.J. Bottomley" <James.Bottomley@HansenPartnership.com>,
"Martin K. Petersen" <martin.petersen@oracle.com>,
Ulf Hansson <ulf.hansson@linaro.org>,
"Neeraj Soni" <neeraj.soni@oss.qualcomm.com>,
Harshal Dev <harshal.dev@oss.qualcomm.com>,
Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>,
Rob Herring <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: <linux-arm-msm@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-scsi@vger.kernel.org>, <linux-mmc@vger.kernel.org>,
<devicetree@vger.kernel.org>,
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Subject: Re: [PATCH v8 3/5] mmc: sdhci-msm: Set ICE clk to TURBO at sdhci ICE init
Date: Tue, 5 May 2026 13:05:51 +0300 [thread overview]
Message-ID: <e0a93b90-5e9e-4856-bc4a-60547282420b@intel.com> (raw)
In-Reply-To: <5ebaeea1-215b-415b-9333-02705ac305f5@intel.com>
On 05/05/2026 13:00, Adrian Hunter wrote:
> On 09/04/2026 14:44, Abhinaba Rakshit wrote:
>> MMC controller lacks a clock scaling mechanism, unlike the UFS
>> controller. By default, the MMC controller is set to TURBO mode
>> during probe, but the ICE clock remains at XO frequency,
>> leading to read/write performance degradation on eMMC.
>>
>> To address this, set the ICE clock to TURBO during sdhci_msm_ice_init
>> to align it with the controller clock. This ensures consistent
>> performance and avoids mismatches between the controller
>> and ICE clock frequencies.
>>
>> For platforms where ICE is represented as a separate device,
>> use the OPP framework to vote for TURBO mode, maintaining
>> proper voltage and power domain constraints.
>>
>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
>
> Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
Or rather:
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
>
>> ---
>> drivers/mmc/host/sdhci-msm.c | 24 ++++++++++++++++++++++++
>> 1 file changed, 24 insertions(+)
>>
>> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
>> index da356627d9de6a11ed5779bf057fa8eb23c38bc0..32e3f37fe425f66c00290a373e06e8ab6257824e 100644
>> --- a/drivers/mmc/host/sdhci-msm.c
>> +++ b/drivers/mmc/host/sdhci-msm.c
>> @@ -1901,6 +1901,8 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
>> #ifdef CONFIG_MMC_CRYPTO
>>
>> static const struct blk_crypto_ll_ops sdhci_msm_crypto_ops; /* forward decl */
>> +static int sdhci_msm_ice_scale_clk(struct sdhci_msm_host *msm_host, unsigned long target_freq,
>> + bool round_ceil); /* forward decl */
>>
>> static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,
>> struct cqhci_host *cq_host)
>> @@ -1964,6 +1966,11 @@ static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,
>> }
>>
>> mmc->caps2 |= MMC_CAP2_CRYPTO;
>> +
>> + err = sdhci_msm_ice_scale_clk(msm_host, INT_MAX, false);
>> + if (err && err != -EOPNOTSUPP)
>> + dev_warn(dev, "Unable to boost ICE clock to TURBO\n");
>> +
>> return 0;
>> }
>>
>> @@ -1989,6 +1996,16 @@ static int sdhci_msm_ice_suspend(struct sdhci_msm_host *msm_host)
>> return 0;
>> }
>>
>> +static int sdhci_msm_ice_scale_clk(struct sdhci_msm_host *msm_host,
>> + unsigned long target_freq,
>> + bool round_ceil)
>> +{
>> + if (msm_host->mmc->caps2 & MMC_CAP2_CRYPTO)
>> + return qcom_ice_scale_clk(msm_host->ice, target_freq, round_ceil);
>> +
>> + return 0;
>> +}
>> +
>> static inline struct sdhci_msm_host *
>> sdhci_msm_host_from_crypto_profile(struct blk_crypto_profile *profile)
>> {
>> @@ -2114,6 +2131,13 @@ sdhci_msm_ice_suspend(struct sdhci_msm_host *msm_host)
>> {
>> return 0;
>> }
>> +
>> +static inline int
>> +sdhci_msm_ice_scale_clk(struct sdhci_msm_host *msm_host, unsigned long target_freq,
>> + bool round_ceil)
>> +{
>> + return 0;
>> +}
>> #endif /* !CONFIG_MMC_CRYPTO */
>>
>> /*****************************************************************************\
>>
>
next prev parent reply other threads:[~2026-05-05 10:06 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-09 11:44 [PATCH v8 0/5] Enable ICE clock scaling Abhinaba Rakshit
2026-04-09 11:44 ` [PATCH v8 1/5] soc: qcom: ice: Add OPP-based clock scaling support for ICE Abhinaba Rakshit
2026-04-17 13:25 ` Harshal Dev
2026-04-21 6:06 ` Abhinaba Rakshit
2026-04-09 11:44 ` [PATCH v8 2/5] ufs: host: Add ICE clock scaling during UFS clock changes Abhinaba Rakshit
2026-04-17 13:32 ` Harshal Dev
2026-04-09 11:44 ` [PATCH v8 3/5] mmc: sdhci-msm: Set ICE clk to TURBO at sdhci ICE init Abhinaba Rakshit
2026-04-17 13:29 ` Harshal Dev
2026-04-21 6:10 ` Abhinaba Rakshit
2026-05-05 10:00 ` Adrian Hunter
2026-05-05 10:05 ` Adrian Hunter [this message]
2026-04-09 11:44 ` [PATCH v8 4/5] arm64: dts: qcom: kodiak: Add OPP-table for ICE UFS and ICE eMMC nodes Abhinaba Rakshit
2026-04-10 10:53 ` Kuldeep Singh
2026-04-21 5:58 ` Abhinaba Rakshit
2026-04-09 11:44 ` [PATCH v8 5/5] arm64: dts: qcom: monaco: " Abhinaba Rakshit
2026-04-10 10:57 ` Kuldeep Singh
2026-04-21 5:50 ` Abhinaba Rakshit
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