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Wed, 07 Oct 2026 04:33:13 -0700 (PDT) X-Received: by 2002:a05:6a00:2188:b0:882:6d80:e5ad with SMTP id d2e1a72fcca58-891b0c83960mr1586011b3a.9.1791372792597; Wed, 07 Oct 2026 04:33:12 -0700 (PDT) Received: from [10.218.41.37] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-89188914299sm1203497b3a.15.2026.10.07.04.33.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 07 Oct 2026 04:33:12 -0700 (PDT) Message-ID: Date: Wed, 7 Oct 2026 17:03:02 +0530 Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 5/5] phy: qcom-qmp-ufs: Add Glymur support To: Dmitry Baryshkov Cc: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Avri Altman , Bart Van Assche , Bjorn Andersson , Konrad Dybcio , gopikrishna.garmidi@oss.qualcomm.com, jagadeesh.kona@oss.qualcomm.com, Abel Vesa , Abel Vesa , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, nitin.rawat@oss.qualcomm.com, sibi.sankar@oss.qualcomm.com, Taniya Das , Konrad Dybcio References: <20261007-glymur_ufs_qcb_enablement-v3-0-84cf4f861415@oss.qualcomm.com> <20261007-glymur_ufs_qcb_enablement-v3-5-84cf4f861415@oss.qualcomm.com> Content-Language: en-US From: Pradeep Pragallapati In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: pORTs0V4mk23YyJSd1F2h_3ryeShy0Fb X-Authority-Analysis: v=2.4 cv=ZZiIpcVA c=1 sm=1 tr=0 ts=6ac62dfa cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=FIX8ga0CBHvb0ZQaSzQA:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDA3MDA0NSBTYWx0ZWRfX55QJ6vxe/CqP d38eERJ3vAi9BlaI2SMa9QCxDKwPIGLF03TV+uLqnjuqHiZGY2y7W45dprTW96+tM8MNRUc1tyZ si9Ir0mobRkA2ROXRhcusP5C/+ypC64= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDA3MDA0NSBTYWx0ZWRfXzHcabIPk4Za6 kU/5Maiy/UBL94jupuHhUYP3vSHTkkcEuGC3yx+XIq4H0FmEkBJq4jDTufGt+ZKHrhTV26sBQPv W73rdKUErQrJNHgN559hHQdYjod5CsIxNoe1xNc+Ndt6+5BRm3NhfCvP3s8WNdhL24HF6cLGL0T tjfiL9yD/SGYVnZL4oZAZlWmaU57PeBE9GwlIurFX4wQGTxfn7T3hn2+6rQ9gnhv/IwxpMNvy1N bVIggRzV7auqGu1dn5VTDpzpiocoFvbfz3MEgBxJ7ZyWw7TGE0D2z47p7XV7DDtNa8a6eMIutk+ xahOoA2dLqVPPVp8sAScRzWsFeqgIhErB+E5ukFo2NahbaHSrYC5wM4JeTB74cXPXyW3KiHyihL s8tAMCKToQZZRCq5b7Ri1/vscNnaaEl6VWfy3aCvk2Dn9UgYYg5xOnZ4xQGIS4I9V0PVJdlStHC CMzVyGODl2bsne7De0g== X-Proofpoint-ORIG-GUID: pORTs0V4mk23YyJSd1F2h_3ryeShy0Fb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-07_04,2026-10-06_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 phishscore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2610070045 On 10/7/2026 1:18 PM, Dmitry Baryshkov wrote: > On Wed, Oct 07, 2026 at 11:59:38AM +0530, Pradeep P V K wrote: >> Add the init sequence tables and config for the UFS QMP phy found in >> the Glymur SoC. >> >> Reviewed-by: Abel Vesa >> Acked-by: Konrad Dybcio >> Signed-off-by: Pradeep P V K >> --- >> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 99 +++++++++++++++++++++++++++++++++ >> 1 file changed, 99 insertions(+) >> >> + .offsets = &qmp_ufs_offsets_v6, > > So, is it a PHY using v6 offsets, but v7 registers inside? > The QSERDES RX0 register offsets on Glymur SoC are aligned with the v7 register layout offsets. Therefore, the v7 QSERDES RX0 register offsets are used for Glymur (similar to SM8750). >> + .max_supported_gear = UFS_HS_G5, >> + >> + .vreg_list = glymur_ufsphy_vreg_l, >> + .num_vregs = ARRAY_SIZE(glymur_ufsphy_vreg_l), >> + .regs = ufsphy_v6_regs_layout, > > v7 > >> +}; >> + >> static const struct qmp_phy_cfg milos_ufsphy_cfg = { >> .lanes = 2, >> >