[PATCH v2 0/3] dt-bindings: ufs: qcom: Split SC7180, SM8650 and similar into separate file

[PATCH v2 0/3] dt-bindings: ufs: qcom: Split SC7180, SM8650 and similar into separate file

[Krzysztof Kozlowski]

Changes in v2:
- Patch #2: rename subject to SC7180 and include SC7180 as well. SC7180
  has one clock less.
- New Patch #3: Split SM8650 and SM8750 to their own file, because these
  are first variants with MCQ.
  Add also MCQ address space, to fully document the hardware.
- Link to v1: https://lore.kernel.org/r/20250730-dt-bindings-ufs-qcom-v1-0-4cec9ff202dc@linaro.org

Description:
The binding for Qualcomm SoC UFS controllers grew and it will grow
further.  It already includes several conditionals, partially for
difference in handling encryption block (ICE, either as phandle or as IO
address space) but it will further grow for MCQ.

See also: lore.kernel.org/r/20250730082229.23475-1-quic_rdwivedi@quicinc.com

The SM8650 is first SoC coming with MCQ, which was missing in the
binding. Document this as well.

Best regards,
Krzysztof

---
Krzysztof Kozlowski (3):
      dt-bindings: ufs: qcom: Split common part to qcom,ufs-common.yaml
      dt-bindings: ufs: qcom: Split SC7180 and similar
      dt-bindings: ufs: qcom: Split SM8650 and similar

 .../devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml | 167 +++++++++++++++++++
 .../devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml | 178 ++++++++++++++++++++
 .../devicetree/bindings/ufs/qcom,ufs-common.yaml   |  67 ++++++++
 .../devicetree/bindings/ufs/qcom,ufs.yaml          | 185 ++++-----------------
 4 files changed, 446 insertions(+), 151 deletions(-)
---
base-commit: d7af19298454ed155f5cf67201a70f5cf836c842
change-id: 20250730-dt-bindings-ufs-qcom-980795ebd0aa

Best regards,
-- 
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

[PATCH v2 1/3] dt-bindings: ufs: qcom: Split common part to qcom,ufs-common.yaml

[Krzysztof Kozlowski]

The binding for Qualcomm SoC UFS controllers grew and it will grow
further.  It already includes several conditionals, partially for
difference in handling encryption block (ICE, either as phandle or as IO
address space) but it will further grow for MCQ.

Prepare for splitting this one big binding into several ones for common
group of devices by defining common part for all Qualcomm UFS schemas.

This only moves code, no functional impact expected.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 .../devicetree/bindings/ufs/qcom,ufs-common.yaml   | 67 ++++++++++++++++++++++
 .../devicetree/bindings/ufs/qcom,ufs.yaml          | 53 +----------------
 2 files changed, 68 insertions(+), 52 deletions(-)

diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs-common.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs-common.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..962dffcd28b44b3489be5615c75e7270a0c45dc4
--- /dev/null
+++ b/Documentation/devicetree/bindings/ufs/qcom,ufs-common.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ufs/qcom,ufs-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Universal Flash Storage (UFS) Controller Common Properties
+
+maintainers:
+  - Bjorn Andersson <bjorn.andersson@linaro.org>
+
+properties:
+  clocks:
+    minItems: 7
+    maxItems: 9
+
+  clock-names:
+    minItems: 7
+    maxItems: 9
+
+  dma-coherent: true
+
+  interconnects:
+    minItems: 2
+    maxItems: 2
+
+  interconnect-names:
+    items:
+      - const: ufs-ddr
+      - const: cpu-ufs
+
+  iommus:
+    minItems: 1
+    maxItems: 2
+
+  phys:
+    maxItems: 1
+
+  phy-names:
+    items:
+      - const: ufsphy
+
+  power-domains:
+    maxItems: 1
+
+  required-opps:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  '#reset-cells':
+    const: 1
+
+  reset-names:
+    items:
+      - const: rst
+
+  reset-gpios:
+    maxItems: 1
+    description:
+      GPIO connected to the RESET pin of the UFS memory device.
+
+allOf:
+  - $ref: ufs-common.yaml
+
+additionalProperties: true
diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
index 6c6043d9809e1d6bf489153ab0aea5186d3563cc..fc0f7b8d1cd1c4a2168f29cffcc0c2ff660424df 100644
--- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
@@ -47,39 +47,6 @@ properties:
       - const: qcom,ufshc
       - const: jedec,ufs-2.0
 
-  clocks:
-    minItems: 7
-    maxItems: 9
-
-  clock-names:
-    minItems: 7
-    maxItems: 9
-
-  dma-coherent: true
-
-  interconnects:
-    minItems: 2
-    maxItems: 2
-
-  interconnect-names:
-    items:
-      - const: ufs-ddr
-      - const: cpu-ufs
-
-  iommus:
-    minItems: 1
-    maxItems: 2
-
-  phys:
-    maxItems: 1
-
-  phy-names:
-    items:
-      - const: ufsphy
-
-  power-domains:
-    maxItems: 1
-
   qcom,ice:
     $ref: /schemas/types.yaml#/definitions/phandle
     description: phandle to the Inline Crypto Engine node
@@ -93,30 +60,12 @@ properties:
       - const: std
       - const: ice
 
-  required-opps:
-    maxItems: 1
-
-  resets:
-    maxItems: 1
-
-  '#reset-cells':
-    const: 1
-
-  reset-names:
-    items:
-      - const: rst
-
-  reset-gpios:
-    maxItems: 1
-    description:
-      GPIO connected to the RESET pin of the UFS memory device.
-
 required:
   - compatible
   - reg
 
 allOf:
-  - $ref: ufs-common.yaml
+  - $ref: qcom,ufs-common.yaml
 
   - if:
       properties:

-- 
2.48.1

[PATCH v2 2/3] dt-bindings: ufs: qcom: Split SC7180 and similar

[Krzysztof Kozlowski]

The binding for Qualcomm SoC UFS controllers grew and it will grow
further.  Split SC7180 and several other devices which:
1. Do not reference ICE as IO address space, but as a phandle,
2. Have same order of clocks (SC7180 has one clock less than SC7280 and
   other variants in split binding).

The split allows easier review and maintenance of the binding.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 .../devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml | 167 +++++++++++++++++++++
 .../devicetree/bindings/ufs/qcom,ufs.yaml          | 104 +++++--------
 2 files changed, 202 insertions(+), 69 deletions(-)

diff --git a/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml b/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..d94ef4e6b85a404c0a1f3c6cfcc10d3da857ce98
--- /dev/null
+++ b/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml
@@ -0,0 +1,167 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ufs/qcom,sc7180-ufshc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SC7180 and Other SoCs UFS Controllers
+
+maintainers:
+  - Bjorn Andersson <bjorn.andersson@linaro.org>
+
+# Select only our matches, not all jedec,ufs-2.0
+select:
+  properties:
+    compatible:
+      contains:
+        enum:
+          - qcom,msm8998-ufshc
+          - qcom,qcs8300-ufshc
+          - qcom,sa8775p-ufshc
+          - qcom,sc7180-ufshc
+          - qcom,sc7280-ufshc
+          - qcom,sc8180x-ufshc
+          - qcom,sc8280xp-ufshc
+          - qcom,sm8250-ufshc
+          - qcom,sm8350-ufshc
+          - qcom,sm8450-ufshc
+          - qcom,sm8550-ufshc
+  required:
+    - compatible
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - qcom,msm8998-ufshc
+          - qcom,qcs8300-ufshc
+          - qcom,sa8775p-ufshc
+          - qcom,sc7180-ufshc
+          - qcom,sc7280-ufshc
+          - qcom,sc8180x-ufshc
+          - qcom,sc8280xp-ufshc
+          - qcom,sm8250-ufshc
+          - qcom,sm8350-ufshc
+          - qcom,sm8450-ufshc
+          - qcom,sm8550-ufshc
+      - const: qcom,ufshc
+      - const: jedec,ufs-2.0
+
+  reg:
+    maxItems: 1
+
+  reg-names:
+    items:
+      - const: std
+
+  clocks:
+    minItems: 7
+    maxItems: 8
+
+  clock-names:
+    minItems: 7
+    items:
+      - const: core_clk
+      - const: bus_aggr_clk
+      - const: iface_clk
+      - const: core_clk_unipro
+      - const: ref_clk
+      - const: tx_lane0_sync_clk
+      - const: rx_lane0_sync_clk
+      - const: rx_lane1_sync_clk
+
+  qcom,ice:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: phandle to the Inline Crypto Engine node
+
+required:
+  - compatible
+  - reg
+
+allOf:
+  - $ref: qcom,ufs-common.yaml
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,sc7180-ufshc
+    then:
+      properties:
+        clocks:
+          maxItems: 7
+        clock-names:
+          maxItems: 7
+    else:
+      properties:
+        clocks:
+          minItems: 8
+        clock-names:
+          minItems: 8
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/gpio/gpio.h>
+    #include <dt-bindings/interconnect/qcom,sm8450.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        ufs@1d84000 {
+            compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
+                         "jedec,ufs-2.0";
+            reg = <0x0 0x01d84000 0x0 0x3000>;
+            interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+            phys = <&ufs_mem_phy_lanes>;
+            phy-names = "ufsphy";
+            lanes-per-direction = <2>;
+            #reset-cells = <1>;
+            resets = <&gcc GCC_UFS_PHY_BCR>;
+            reset-names = "rst";
+            reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
+
+            vcc-supply = <&vreg_l7b_2p5>;
+            vcc-max-microamp = <1100000>;
+            vccq-supply = <&vreg_l9b_1p2>;
+            vccq-max-microamp = <1200000>;
+
+            power-domains = <&gcc UFS_PHY_GDSC>;
+            iommus = <&apps_smmu 0xe0 0x0>;
+            interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
+                            <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
+            interconnect-names = "ufs-ddr", "cpu-ufs";
+
+            clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+                     <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+                     <&gcc GCC_UFS_PHY_AHB_CLK>,
+                     <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+                     <&rpmhcc RPMH_CXO_CLK>,
+                     <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+                     <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+                     <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+            clock-names = "core_clk",
+                          "bus_aggr_clk",
+                          "iface_clk",
+                          "core_clk_unipro",
+                          "ref_clk",
+                          "tx_lane0_sync_clk",
+                          "rx_lane0_sync_clk",
+                          "rx_lane1_sync_clk";
+            freq-table-hz = <75000000 300000000>,
+                            <0 0>,
+                            <0 0>,
+                            <75000000 300000000>,
+                            <75000000 300000000>,
+                            <0 0>,
+                            <0 0>,
+                            <0 0>;
+            qcom,ice = <&ice>;
+        };
+    };
diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
index fc0f7b8d1cd1c4a2168f29cffcc0c2ff660424df..191b88120d139a47632e3dce3d3f3a37d7a55c72 100644
--- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
@@ -15,7 +15,17 @@ select:
   properties:
     compatible:
       contains:
-        const: qcom,ufshc
+        enum:
+          - qcom,msm8994-ufshc
+          - qcom,msm8996-ufshc
+          - qcom,qcs615-ufshc
+          - qcom,sdm845-ufshc
+          - qcom,sm6115-ufshc
+          - qcom,sm6125-ufshc
+          - qcom,sm6350-ufshc
+          - qcom,sm8150-ufshc
+          - qcom,sm8650-ufshc
+          - qcom,sm8750-ufshc
   required:
     - compatible
 
@@ -25,23 +35,12 @@ properties:
       - enum:
           - qcom,msm8994-ufshc
           - qcom,msm8996-ufshc
-          - qcom,msm8998-ufshc
           - qcom,qcs615-ufshc
-          - qcom,qcs8300-ufshc
-          - qcom,sa8775p-ufshc
-          - qcom,sc7180-ufshc
-          - qcom,sc7280-ufshc
-          - qcom,sc8180x-ufshc
-          - qcom,sc8280xp-ufshc
           - qcom,sdm845-ufshc
           - qcom,sm6115-ufshc
           - qcom,sm6125-ufshc
           - qcom,sm6350-ufshc
           - qcom,sm8150-ufshc
-          - qcom,sm8250-ufshc
-          - qcom,sm8350-ufshc
-          - qcom,sm8450-ufshc
-          - qcom,sm8550-ufshc
           - qcom,sm8650-ufshc
           - qcom,sm8750-ufshc
       - const: qcom,ufshc
@@ -72,41 +71,6 @@ allOf:
         compatible:
           contains:
             enum:
-              - qcom,sc7180-ufshc
-    then:
-      properties:
-        clocks:
-          minItems: 7
-          maxItems: 7
-        clock-names:
-          items:
-            - const: core_clk
-            - const: bus_aggr_clk
-            - const: iface_clk
-            - const: core_clk_unipro
-            - const: ref_clk
-            - const: tx_lane0_sync_clk
-            - const: rx_lane0_sync_clk
-        reg:
-          maxItems: 1
-        reg-names:
-          maxItems: 1
-
-  - if:
-      properties:
-        compatible:
-          contains:
-            enum:
-              - qcom,msm8998-ufshc
-              - qcom,qcs8300-ufshc
-              - qcom,sa8775p-ufshc
-              - qcom,sc7280-ufshc
-              - qcom,sc8180x-ufshc
-              - qcom,sc8280xp-ufshc
-              - qcom,sm8250-ufshc
-              - qcom,sm8350-ufshc
-              - qcom,sm8450-ufshc
-              - qcom,sm8550-ufshc
               - qcom,sm8650-ufshc
               - qcom,sm8750-ufshc
     then:
@@ -246,10 +210,10 @@ unevaluatedProperties: false
 
 examples:
   - |
-    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
+    #include <dt-bindings/clock/qcom,gcc-sm8150.h>
     #include <dt-bindings/clock/qcom,rpmh.h>
     #include <dt-bindings/gpio/gpio.h>
-    #include <dt-bindings/interconnect/qcom,sm8450.h>
+    #include <dt-bindings/interconnect/qcom,sm8150.h>
     #include <dt-bindings/interrupt-controller/arm-gic.h>
 
     soc {
@@ -257,9 +221,12 @@ examples:
         #size-cells = <2>;
 
         ufs@1d84000 {
-            compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
+            compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
                          "jedec,ufs-2.0";
-            reg = <0 0x01d84000 0 0x3000>;
+            reg = <0x0 0x01d84000 0x0 0x2500>,
+                  <0x0 0x01d90000 0x0 0x8000>;
+            reg-names = "std", "ice";
+
             interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
             phys = <&ufs_mem_phy_lanes>;
             phy-names = "ufsphy";
@@ -275,19 +242,8 @@ examples:
             vccq-max-microamp = <1200000>;
 
             power-domains = <&gcc UFS_PHY_GDSC>;
-            iommus = <&apps_smmu 0xe0 0x0>;
-            interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
-                            <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
-            interconnect-names = "ufs-ddr", "cpu-ufs";
+            iommus = <&apps_smmu 0x300 0>;
 
-            clock-names = "core_clk",
-                          "bus_aggr_clk",
-                          "iface_clk",
-                          "core_clk_unipro",
-                          "ref_clk",
-                          "tx_lane0_sync_clk",
-                          "rx_lane0_sync_clk",
-                          "rx_lane1_sync_clk";
             clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
                      <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
                      <&gcc GCC_UFS_PHY_AHB_CLK>,
@@ -295,15 +251,25 @@ examples:
                      <&rpmhcc RPMH_CXO_CLK>,
                      <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
                      <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
-                     <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
-            freq-table-hz = <75000000 300000000>,
+                     <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
+                     <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+            clock-names = "core_clk",
+                          "bus_aggr_clk",
+                          "iface_clk",
+                          "core_clk_unipro",
+                          "ref_clk",
+                          "tx_lane0_sync_clk",
+                          "rx_lane0_sync_clk",
+                          "rx_lane1_sync_clk",
+                          "ice_core_clk";
+            freq-table-hz = <37500000 300000000>,
                             <0 0>,
                             <0 0>,
-                            <75000000 300000000>,
-                            <75000000 300000000>,
+                            <37500000 300000000>,
                             <0 0>,
                             <0 0>,
-                            <0 0>;
-            qcom,ice = <&ice>;
+                            <0 0>,
+                            <0 0>,
+                            <0 300000000>;
         };
     };

-- 
2.48.1

[PATCH v2 3/3] dt-bindings: ufs: qcom: Split SM8650 and similar

[Krzysztof Kozlowski]

The binding for Qualcomm SoC UFS controllers grew and it will grow
further.  Split SM8650 and SM8750 UFS controllers which:
1. Do not reference ICE as IO address space, but as phandle,
2. Have same order of clocks.
3. Have MCQ IO address space. Document that MCQ address space as
   optional to maintain backwards compatibility and because Linux
   drivers can operate perfectly fine without it (thus without MCQ
   feature).  Linux driver already uses "mcq" as possible name for
   "reg-names" property.

The split allows easier review and maintenance of the binding.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 .../devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml | 178 +++++++++++++++++++++
 .../devicetree/bindings/ufs/qcom,ufs.yaml          |  32 ----
 2 files changed, 178 insertions(+), 32 deletions(-)

diff --git a/Documentation/devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml b/Documentation/devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..aaa0bbb5bfe1673e3e0d25812c2829350b137abb
--- /dev/null
+++ b/Documentation/devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml
@@ -0,0 +1,178 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ufs/qcom,sm8650-ufshc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8650 and Other SoCs UFS Controllers
+
+maintainers:
+  - Bjorn Andersson <bjorn.andersson@linaro.org>
+
+# Select only our matches, not all jedec,ufs-2.0
+select:
+  properties:
+    compatible:
+      contains:
+        enum:
+          - qcom,sm8650-ufshc
+          - qcom,sm8750-ufshc
+  required:
+    - compatible
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - qcom,sm8650-ufshc
+          - qcom,sm8750-ufshc
+      - const: qcom,ufshc
+      - const: jedec,ufs-2.0
+
+  reg:
+    minItems: 1
+    maxItems: 2
+
+  reg-names:
+    minItems: 1
+    items:
+      - const: std
+      - const: mcq
+
+  clocks:
+    minItems: 8
+    maxItems: 8
+
+  clock-names:
+    items:
+      - const: core_clk
+      - const: bus_aggr_clk
+      - const: iface_clk
+      - const: core_clk_unipro
+      - const: ref_clk
+      - const: tx_lane0_sync_clk
+      - const: rx_lane0_sync_clk
+      - const: rx_lane1_sync_clk
+
+  qcom,ice:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: phandle to the Inline Crypto Engine node
+
+required:
+  - compatible
+  - reg
+
+allOf:
+  - $ref: qcom,ufs-common.yaml
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,sm8650-gcc.h>
+    #include <dt-bindings/clock/qcom,sm8650-tcsr.h>
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/gpio/gpio.h>
+    #include <dt-bindings/interconnect/qcom,icc.h>
+    #include <dt-bindings/interconnect/qcom,sm8650-rpmh.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        ufshc@1d84000 {
+            compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
+            reg = <0x0 0x01d84000 0x0 0x3000>;
+
+            interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
+
+            clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+                     <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+                     <&gcc GCC_UFS_PHY_AHB_CLK>,
+                     <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+                     <&tcsr TCSR_UFS_PAD_CLKREF_EN>,
+                     <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+                     <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+                     <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+            clock-names = "core_clk",
+                          "bus_aggr_clk",
+                          "iface_clk",
+                          "core_clk_unipro",
+                          "ref_clk",
+                          "tx_lane0_sync_clk",
+                          "rx_lane0_sync_clk",
+                          "rx_lane1_sync_clk";
+
+            resets = <&gcc GCC_UFS_PHY_BCR>;
+            reset-names = "rst";
+            reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
+
+            interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
+                             &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+                            <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+                             &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+            interconnect-names = "ufs-ddr",
+                         "cpu-ufs";
+
+            power-domains = <&gcc UFS_PHY_GDSC>;
+            required-opps = <&rpmhpd_opp_nom>;
+
+            operating-points-v2 = <&ufs_opp_table>;
+
+            iommus = <&apps_smmu 0x60 0>;
+
+            lanes-per-direction = <2>;
+            qcom,ice = <&ice>;
+
+            phys = <&ufs_mem_phy>;
+            phy-names = "ufsphy";
+
+            #reset-cells = <1>;
+
+            vcc-supply = <&vreg_l7b_2p5>;
+            vcc-max-microamp = <1100000>;
+            vccq-supply = <&vreg_l9b_1p2>;
+            vccq-max-microamp = <1200000>;
+
+            ufs_opp_table: opp-table {
+                compatible = "operating-points-v2";
+
+                opp-100000000 {
+                    opp-hz = /bits/ 64 <100000000>,
+                             /bits/ 64 <0>,
+                             /bits/ 64 <0>,
+                             /bits/ 64 <100000000>,
+                             /bits/ 64 <0>,
+                             /bits/ 64 <0>,
+                             /bits/ 64 <0>,
+                             /bits/ 64 <0>;
+                    required-opps = <&rpmhpd_opp_low_svs>;
+                };
+
+                opp-201500000 {
+                    opp-hz = /bits/ 64 <201500000>,
+                             /bits/ 64 <0>,
+                             /bits/ 64 <0>,
+                             /bits/ 64 <201500000>,
+                             /bits/ 64 <0>,
+                             /bits/ 64 <0>,
+                             /bits/ 64 <0>,
+                             /bits/ 64 <0>;
+                    required-opps = <&rpmhpd_opp_svs>;
+                };
+
+                opp-403000000 {
+                    opp-hz = /bits/ 64 <403000000>,
+                             /bits/ 64 <0>,
+                             /bits/ 64 <0>,
+                             /bits/ 64 <403000000>,
+                             /bits/ 64 <0>,
+                             /bits/ 64 <0>,
+                             /bits/ 64 <0>,
+                             /bits/ 64 <0>;
+                    required-opps = <&rpmhpd_opp_nom>;
+                };
+            };
+        };
+    };
diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
index 191b88120d139a47632e3dce3d3f3a37d7a55c72..1dd41f6d5258014d59c8c8005bc54f7994351a52 100644
--- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
@@ -24,8 +24,6 @@ select:
           - qcom,sm6125-ufshc
           - qcom,sm6350-ufshc
           - qcom,sm8150-ufshc
-          - qcom,sm8650-ufshc
-          - qcom,sm8750-ufshc
   required:
     - compatible
 
@@ -41,8 +39,6 @@ properties:
           - qcom,sm6125-ufshc
           - qcom,sm6350-ufshc
           - qcom,sm8150-ufshc
-          - qcom,sm8650-ufshc
-          - qcom,sm8750-ufshc
       - const: qcom,ufshc
       - const: jedec,ufs-2.0
 
@@ -66,34 +62,6 @@ required:
 allOf:
   - $ref: qcom,ufs-common.yaml
 
-  - if:
-      properties:
-        compatible:
-          contains:
-            enum:
-              - qcom,sm8650-ufshc
-              - qcom,sm8750-ufshc
-    then:
-      properties:
-        clocks:
-          minItems: 8
-          maxItems: 8
-        clock-names:
-          items:
-            - const: core_clk
-            - const: bus_aggr_clk
-            - const: iface_clk
-            - const: core_clk_unipro
-            - const: ref_clk
-            - const: tx_lane0_sync_clk
-            - const: rx_lane0_sync_clk
-            - const: rx_lane1_sync_clk
-        reg:
-          minItems: 1
-          maxItems: 1
-        reg-names:
-          maxItems: 1
-
   - if:
       properties:
         compatible:

-- 
2.48.1

Re: [PATCH v2 1/3] dt-bindings: ufs: qcom: Split common part to qcom,ufs-common.yaml

[Rob Herring (Arm)]

On Thu, 31 Jul 2025 09:15:52 +0200, Krzysztof Kozlowski wrote:
> The binding for Qualcomm SoC UFS controllers grew and it will grow
> further.  It already includes several conditionals, partially for
> difference in handling encryption block (ICE, either as phandle or as IO
> address space) but it will further grow for MCQ.
> 
> Prepare for splitting this one big binding into several ones for common
> group of devices by defining common part for all Qualcomm UFS schemas.
> 
> This only moves code, no functional impact expected.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
>  .../devicetree/bindings/ufs/qcom,ufs-common.yaml   | 67 ++++++++++++++++++++++
>  .../devicetree/bindings/ufs/qcom,ufs.yaml          | 53 +----------------
>  2 files changed, 68 insertions(+), 52 deletions(-)
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH v2 2/3] dt-bindings: ufs: qcom: Split SC7180 and similar

[Rob Herring (Arm)]

On Thu, 31 Jul 2025 09:15:53 +0200, Krzysztof Kozlowski wrote:
> The binding for Qualcomm SoC UFS controllers grew and it will grow
> further.  Split SC7180 and several other devices which:
> 1. Do not reference ICE as IO address space, but as a phandle,
> 2. Have same order of clocks (SC7180 has one clock less than SC7280 and
>    other variants in split binding).
> 
> The split allows easier review and maintenance of the binding.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
>  .../devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml | 167 +++++++++++++++++++++
>  .../devicetree/bindings/ufs/qcom,ufs.yaml          | 104 +++++--------
>  2 files changed, 202 insertions(+), 69 deletions(-)
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH v2 3/3] dt-bindings: ufs: qcom: Split SM8650 and similar

[Rob Herring (Arm)]

On Thu, 31 Jul 2025 09:15:54 +0200, Krzysztof Kozlowski wrote:
> The binding for Qualcomm SoC UFS controllers grew and it will grow
> further.  Split SM8650 and SM8750 UFS controllers which:
> 1. Do not reference ICE as IO address space, but as phandle,
> 2. Have same order of clocks.
> 3. Have MCQ IO address space. Document that MCQ address space as
>    optional to maintain backwards compatibility and because Linux
>    drivers can operate perfectly fine without it (thus without MCQ
>    feature).  Linux driver already uses "mcq" as possible name for
>    "reg-names" property.
> 
> The split allows easier review and maintenance of the binding.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
>  .../devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml | 178 +++++++++++++++++++++
>  .../devicetree/bindings/ufs/qcom,ufs.yaml          |  32 ----
>  2 files changed, 178 insertions(+), 32 deletions(-)
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH v2 3/3] dt-bindings: ufs: qcom: Split SM8650 and similar

[Manivannan Sadhasivam]

On Thu, Jul 31, 2025 at 09:15:54AM GMT, Krzysztof Kozlowski wrote:
> The binding for Qualcomm SoC UFS controllers grew and it will grow
> further.  Split SM8650 and SM8750 UFS controllers which:
> 1. Do not reference ICE as IO address space, but as phandle,
> 2. Have same order of clocks.
> 3. Have MCQ IO address space. Document that MCQ address space as
>    optional to maintain backwards compatibility and because Linux
>    drivers can operate perfectly fine without it (thus without MCQ
>    feature).  Linux driver already uses "mcq" as possible name for
>    "reg-names" property.

Since Qcom SoC memory maps have holes and shared registers in the whole 'mcq'
region, it is preferred to map only the required parts. So please drop 'mcq' and
add 'mcq_sqd', 'mcq_vs' regions.

With the above change, 

Acked-by: Manivannan Sadhasivam <mani@kernel.org>

- Mani

> 
> The split allows easier review and maintenance of the binding.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
>  .../devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml | 178 +++++++++++++++++++++
>  .../devicetree/bindings/ufs/qcom,ufs.yaml          |  32 ----
>  2 files changed, 178 insertions(+), 32 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml b/Documentation/devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..aaa0bbb5bfe1673e3e0d25812c2829350b137abb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml
> @@ -0,0 +1,178 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/ufs/qcom,sm8650-ufshc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm SM8650 and Other SoCs UFS Controllers
> +
> +maintainers:
> +  - Bjorn Andersson <bjorn.andersson@linaro.org>
> +
> +# Select only our matches, not all jedec,ufs-2.0
> +select:
> +  properties:
> +    compatible:
> +      contains:
> +        enum:
> +          - qcom,sm8650-ufshc
> +          - qcom,sm8750-ufshc
> +  required:
> +    - compatible
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - qcom,sm8650-ufshc
> +          - qcom,sm8750-ufshc
> +      - const: qcom,ufshc
> +      - const: jedec,ufs-2.0
> +
> +  reg:
> +    minItems: 1
> +    maxItems: 2
> +
> +  reg-names:
> +    minItems: 1
> +    items:
> +      - const: std
> +      - const: mcq
> +
> +  clocks:
> +    minItems: 8
> +    maxItems: 8
> +
> +  clock-names:
> +    items:
> +      - const: core_clk
> +      - const: bus_aggr_clk
> +      - const: iface_clk
> +      - const: core_clk_unipro
> +      - const: ref_clk
> +      - const: tx_lane0_sync_clk
> +      - const: rx_lane0_sync_clk
> +      - const: rx_lane1_sync_clk
> +
> +  qcom,ice:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description: phandle to the Inline Crypto Engine node
> +
> +required:
> +  - compatible
> +  - reg
> +
> +allOf:
> +  - $ref: qcom,ufs-common.yaml
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/qcom,sm8650-gcc.h>
> +    #include <dt-bindings/clock/qcom,sm8650-tcsr.h>
> +    #include <dt-bindings/clock/qcom,rpmh.h>
> +    #include <dt-bindings/gpio/gpio.h>
> +    #include <dt-bindings/interconnect/qcom,icc.h>
> +    #include <dt-bindings/interconnect/qcom,sm8650-rpmh.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    soc {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +
> +        ufshc@1d84000 {
> +            compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
> +            reg = <0x0 0x01d84000 0x0 0x3000>;
> +
> +            interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
> +
> +            clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
> +                     <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
> +                     <&gcc GCC_UFS_PHY_AHB_CLK>,
> +                     <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
> +                     <&tcsr TCSR_UFS_PAD_CLKREF_EN>,
> +                     <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
> +                     <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
> +                     <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
> +            clock-names = "core_clk",
> +                          "bus_aggr_clk",
> +                          "iface_clk",
> +                          "core_clk_unipro",
> +                          "ref_clk",
> +                          "tx_lane0_sync_clk",
> +                          "rx_lane0_sync_clk",
> +                          "rx_lane1_sync_clk";
> +
> +            resets = <&gcc GCC_UFS_PHY_BCR>;
> +            reset-names = "rst";
> +            reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
> +
> +            interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
> +                             &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> +                            <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> +                             &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
> +            interconnect-names = "ufs-ddr",
> +                         "cpu-ufs";
> +
> +            power-domains = <&gcc UFS_PHY_GDSC>;
> +            required-opps = <&rpmhpd_opp_nom>;
> +
> +            operating-points-v2 = <&ufs_opp_table>;
> +
> +            iommus = <&apps_smmu 0x60 0>;
> +
> +            lanes-per-direction = <2>;
> +            qcom,ice = <&ice>;
> +
> +            phys = <&ufs_mem_phy>;
> +            phy-names = "ufsphy";
> +
> +            #reset-cells = <1>;
> +
> +            vcc-supply = <&vreg_l7b_2p5>;
> +            vcc-max-microamp = <1100000>;
> +            vccq-supply = <&vreg_l9b_1p2>;
> +            vccq-max-microamp = <1200000>;
> +
> +            ufs_opp_table: opp-table {
> +                compatible = "operating-points-v2";
> +
> +                opp-100000000 {
> +                    opp-hz = /bits/ 64 <100000000>,
> +                             /bits/ 64 <0>,
> +                             /bits/ 64 <0>,
> +                             /bits/ 64 <100000000>,
> +                             /bits/ 64 <0>,
> +                             /bits/ 64 <0>,
> +                             /bits/ 64 <0>,
> +                             /bits/ 64 <0>;
> +                    required-opps = <&rpmhpd_opp_low_svs>;
> +                };
> +
> +                opp-201500000 {
> +                    opp-hz = /bits/ 64 <201500000>,
> +                             /bits/ 64 <0>,
> +                             /bits/ 64 <0>,
> +                             /bits/ 64 <201500000>,
> +                             /bits/ 64 <0>,
> +                             /bits/ 64 <0>,
> +                             /bits/ 64 <0>,
> +                             /bits/ 64 <0>;
> +                    required-opps = <&rpmhpd_opp_svs>;
> +                };
> +
> +                opp-403000000 {
> +                    opp-hz = /bits/ 64 <403000000>,
> +                             /bits/ 64 <0>,
> +                             /bits/ 64 <0>,
> +                             /bits/ 64 <403000000>,
> +                             /bits/ 64 <0>,
> +                             /bits/ 64 <0>,
> +                             /bits/ 64 <0>,
> +                             /bits/ 64 <0>;
> +                    required-opps = <&rpmhpd_opp_nom>;
> +                };
> +            };
> +        };
> +    };
> diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
> index 191b88120d139a47632e3dce3d3f3a37d7a55c72..1dd41f6d5258014d59c8c8005bc54f7994351a52 100644
> --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
> +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
> @@ -24,8 +24,6 @@ select:
>            - qcom,sm6125-ufshc
>            - qcom,sm6350-ufshc
>            - qcom,sm8150-ufshc
> -          - qcom,sm8650-ufshc
> -          - qcom,sm8750-ufshc
>    required:
>      - compatible
>  
> @@ -41,8 +39,6 @@ properties:
>            - qcom,sm6125-ufshc
>            - qcom,sm6350-ufshc
>            - qcom,sm8150-ufshc
> -          - qcom,sm8650-ufshc
> -          - qcom,sm8750-ufshc
>        - const: qcom,ufshc
>        - const: jedec,ufs-2.0
>  
> @@ -66,34 +62,6 @@ required:
>  allOf:
>    - $ref: qcom,ufs-common.yaml
>  
> -  - if:
> -      properties:
> -        compatible:
> -          contains:
> -            enum:
> -              - qcom,sm8650-ufshc
> -              - qcom,sm8750-ufshc
> -    then:
> -      properties:
> -        clocks:
> -          minItems: 8
> -          maxItems: 8
> -        clock-names:
> -          items:
> -            - const: core_clk
> -            - const: bus_aggr_clk
> -            - const: iface_clk
> -            - const: core_clk_unipro
> -            - const: ref_clk
> -            - const: tx_lane0_sync_clk
> -            - const: rx_lane0_sync_clk
> -            - const: rx_lane1_sync_clk
> -        reg:
> -          minItems: 1
> -          maxItems: 1
> -        reg-names:
> -          maxItems: 1
> -
>    - if:
>        properties:
>          compatible:
> 
> -- 
> 2.48.1
> 

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v2 3/3] dt-bindings: ufs: qcom: Split SM8650 and similar

[Krzysztof Kozlowski]

On 01/08/2025 14:28, Manivannan Sadhasivam wrote:
> On Thu, Jul 31, 2025 at 09:15:54AM GMT, Krzysztof Kozlowski wrote:
>> The binding for Qualcomm SoC UFS controllers grew and it will grow
>> further.  Split SM8650 and SM8750 UFS controllers which:
>> 1. Do not reference ICE as IO address space, but as phandle,
>> 2. Have same order of clocks.
>> 3. Have MCQ IO address space. Document that MCQ address space as
>>    optional to maintain backwards compatibility and because Linux
>>    drivers can operate perfectly fine without it (thus without MCQ
>>    feature).  Linux driver already uses "mcq" as possible name for
>>    "reg-names" property.
> 
> Since Qcom SoC memory maps have holes and shared registers in the whole 'mcq'
> region, it is preferred to map only the required parts. So please drop 'mcq' and
> add 'mcq_sqd', 'mcq_vs' regions.


No, it is not preferred. The docs are clearly stating that there is oone
address space for MCQ and continuous.

We have been fixing above approach you propose also for other devices,
so this should not go to the broken part.


Best regards,
Krzysztof

Re: [PATCH v2 0/3] dt-bindings: ufs: qcom: Split SC7180, SM8650 and similar into separate file

[Martin K. Petersen]

Krzysztof,

> The binding for Qualcomm SoC UFS controllers grew and it will grow
> further. It already includes several conditionals, partially for
> difference in handling encryption block (ICE, either as phandle or as
> IO address space) but it will further grow for MCQ.

Which tree did you intend to route this through?

-- 
Martin K. Petersen

Re: [PATCH v2 0/3] dt-bindings: ufs: qcom: Split SC7180, SM8650 and similar into separate file

[Krzysztof Kozlowski]

On 06/08/2025 04:37, Martin K. Petersen wrote:
> 
> Krzysztof,
> 
>> The binding for Qualcomm SoC UFS controllers grew and it will grow
>> further. It already includes several conditionals, partially for
>> difference in handling encryption block (ICE, either as phandle or as
>> IO address space) but it will further grow for MCQ.
> 
> Which tree did you intend to route this through?


These are bindings, so please take them via UFS tree. Just like with
every other driver or bindings patch.

Best regards,
Krzysztof

Re: [PATCH v2 0/3] dt-bindings: ufs: qcom: Split SC7180, SM8650 and similar into separate file

[Krzysztof Kozlowski]

On 06/08/2025 07:58, Krzysztof Kozlowski wrote:
> On 06/08/2025 04:37, Martin K. Petersen wrote:
>>
>> Krzysztof,
>>
>>> The binding for Qualcomm SoC UFS controllers grew and it will grow
>>> further. It already includes several conditionals, partially for
>>> difference in handling encryption block (ICE, either as phandle or as
>>> IO address space) but it will further grow for MCQ.
>>
>> Which tree did you intend to route this through?
> 
> 
> These are bindings, so please take them via UFS tree. Just like with
> every other driver or bindings patch.


Hi Martin,

Did my answer reach you? Any questions about applying/merging?

Best regards,
Krzysztof

Re: [PATCH v2 0/3] dt-bindings: ufs: qcom: Split SC7180, SM8650 and similar into separate file

[Martin K. Petersen]

Krzysztof,

> Did my answer reach you? Any questions about applying/merging?

I'm planning on merging the series later today.

-- 
Martin K. Petersen

Re: [PATCH v2 0/3] dt-bindings: ufs: qcom: Split SC7180, SM8650 and similar into separate file

[Martin K. Petersen]

Krzysztof,

> The binding for Qualcomm SoC UFS controllers grew and it will grow
> further. It already includes several conditionals, partially for
> difference in handling encryption block (ICE, either as phandle or as
> IO address space) but it will further grow for MCQ.

Applied to 6.18/scsi-staging, thanks!

-- 
Martin K. Petersen