Re: [PATCH 1/3] tpm: Disable TCG_TPM2_HMAC by default

[Vitor Soares <ivitro@gmail.com>]

On Wed, 2024-05-22 at 14:17 +0100, Vitor Soares wrote:
> On Wed, 2024-05-22 at 15:01 +0300, Jarkko Sakkinen wrote:
> > On Wed May 22, 2024 at 11:18 AM EEST, Vitor Soares wrote:
> > > On Tue, 2024-05-21 at 08:33 -0400, James Bottomley wrote:
> > > > On Tue, 2024-05-21 at 10:10 +0300, Jarkko Sakkinen wrote:
> > > > > This benchmark could be done in user space using /dev/tpm0.
> > > > 
> > > > Let's actually try that.  If you have the ibmtss installed, the command
> > > > to time primary key generation from userspace on your tpm is
> > > > 
> > > > time tsscreateprimary -hi n -ecc nistp256
> > > > 
> > > > 
> > > > And just for chuckles and grins, try it in the owner hierarchy as well
> > > > (sometimes slow TPMs cache this)
> > > > 
> > > > time tsscreateprimary -hi o -ecc nistp256
> > > > 
> > > > And if you have tpm2 tools, the above commands should be:
> > > > 
> > > > time tpm2_createprimary -C n -G ecc256
> > > > time tpm2_createprimary -C o -G ecc256
> > > > 
> > > > James
> > > > 
> > > > 
> > > 
> > > Testing on an arm64 platform I get the following results.
> > 
> > OK, appreciate these results. I try to get mine this week, if I can
> > allocate some bandwidth but latest early next week. The Intel CPU
> > I'll be testing is Intel Celeron J4025:
> > 
> > https://www.intel.com/content/www/us/en/products/sku/197307/intel-celeron-processor-j4025-4m-cache-up-to-2-90-ghz/specifications.html
> > 
> > So if things work reasonably fast with this, then I think we can
> > enable the feature at least on X86_64 by default, and make it
> > opt-in for other arch's.
> > 
> > I sent already this patch but holding with PR up until rc1 is
> > out so that there is some window to act:
> > 
> > https://lore.kernel.org/linux-integrity/20240521130921.15028-1-jarkko@kernel.org/
> > 
> > If I need to send an updated patch ("default X86_64") and rip
> > transcrip from below results.
> > 
> > But to do that correctly I'd need to know at least:
> > 
> > 1. What is the aarch64 platform you are using?
> 
> I was testing this on the Toradex Verdin iMX8MM SoM.
> 
> > 2. What kind of TPM you are using and how is it connect?
> 
> TPM device is the ATTPM20P connect through the SPI at speed of 36 MHz.
> The bus is shared with a CAN controller (MCP251xFD), so both mues work
> together.
> 
> The dts looks like:
> tpm1: tpm@1 {
>         compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
>         interrupts-extended = <&gpio1 7 IRQ_TYPE_LEVEL_LOW>;
>         pinctrl-0 = <&pinctrl_can2_int>;
>         pinctrl-names = "default";
>         reg = <1>;
>         spi-max-frequency = <36000000>;
> };
> 
> Regards,
> Vitor Soares

For the sake of clarity, the timing tests were done without CAN enabled.

> 
> > 
> > Obviously if I make this decision, I'll put you as "Reported-by".
> > 
> > 
>