* [PATCH] tty: xuartps: Fix tx_emtpy() callback
@ 2014-09-05 7:45 Lars-Peter Clausen
2014-09-05 15:52 ` Sören Brinkmann
0 siblings, 1 reply; 2+ messages in thread
From: Lars-Peter Clausen @ 2014-09-05 7:45 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: Michal Simek, Soren Brinkmann, linux-serial, Lars-Peter Clausen
The tx_empty() callback currently checks the TXEMPTY bit in the interrupt
status register to decided whether the FIFO should be reported as empty or
not. The bit in this register gets set when the FIFO state transitions from
non-empty to empty but is cleared again in the interrupt handler. This means
it is not suitable to be used to decided whether the FIFO is currently empty
or not. Instead use the TXEMPTY bit from the status register which will be
set as long as the FIFO is empty.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
drivers/tty/serial/xilinx_uartps.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/tty/serial/xilinx_uartps.c b/drivers/tty/serial/xilinx_uartps.c
index 01951d2..806e4bc 100644
--- a/drivers/tty/serial/xilinx_uartps.c
+++ b/drivers/tty/serial/xilinx_uartps.c
@@ -581,7 +581,7 @@ static unsigned int cdns_uart_tx_empty(struct uart_port *port)
{
unsigned int status;
- status = cdns_uart_readl(CDNS_UART_ISR_OFFSET) & CDNS_UART_IXR_TXEMPTY;
+ status = cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_TXEMPTY;
return status ? TIOCSER_TEMT : 0;
}
--
1.8.0
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH] tty: xuartps: Fix tx_emtpy() callback
2014-09-05 7:45 [PATCH] tty: xuartps: Fix tx_emtpy() callback Lars-Peter Clausen
@ 2014-09-05 15:52 ` Sören Brinkmann
0 siblings, 0 replies; 2+ messages in thread
From: Sören Brinkmann @ 2014-09-05 15:52 UTC (permalink / raw)
To: Lars-Peter Clausen; +Cc: Greg Kroah-Hartman, Michal Simek, linux-serial
On Fri, 2014-09-05 at 09:45AM +0200, Lars-Peter Clausen wrote:
> The tx_empty() callback currently checks the TXEMPTY bit in the interrupt
> status register to decided whether the FIFO should be reported as empty or
> not. The bit in this register gets set when the FIFO state transitions from
> non-empty to empty but is cleared again in the interrupt handler. This means
> it is not suitable to be used to decided whether the FIFO is currently empty
> or not. Instead use the TXEMPTY bit from the status register which will be
> set as long as the FIFO is empty.
>
> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Sören
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