From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Kefeng Wang <wangkefeng.wang@huawei.com>,
Noam Camus <noamc@ezchip.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com>,
linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org,
guohanjun@huawei.com, xuwei5@hisilicon.com
Subject: Re: [PATCH v4] serial: 8250_dw: fix wrong logic in dw8250_check_lcr()
Date: Tue, 05 Apr 2016 13:50:07 +0300 [thread overview]
Message-ID: <1459853407.12843.7.camel@linux.intel.com> (raw)
In-Reply-To: <1459835585-25751-1-git-send-email-wangkefeng.wang@huawei.com>
On Tue, 2016-04-05 at 13:53 +0800, Kefeng Wang wrote:
> Commit cdcea058e510 ("serial: 8250_dw: Avoid serial_outx code
> duplicate
> with new dw8250_check_lcr()") introduce a wrong logic when write val
> to
> LCR reg. When CONFIG_64BIT enabled, __raw_writeq is used
> unconditionally.
>
> The __raw_readq/__raw_writeq is introduced by commit bca2092d7897
> ("serial:
> 8250_dw: Use 64-bit access for OCTEON.") for OCTEON, so for
> !PORT_OCTEON,
> we better to use coincident write func.
>
> Fixes: cdcea058e510("serial: 8250_dw: Avoid serial_outx code
> duplicate with new dw8250_check_lcr()")
> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
> ---
>
> Changes since v3:
> - Add patch change log, suggested by Greg Kroah-Hartman.
> Changes since v2:
> - Add #ifdef CONFIG_64BIT back, ensure it can be built under
Oh, true. Since it's a native IO we can't use writeq() helper from io-
64-nonatomic-*.
> configuration lacking readq/writeq.
> Changes since v1:
> - Repace '#ifdef CONFIG_64BIT' with IS_ENABLED(CONFIG_64BIT).
> - Enrich patch log, and add Fixes tag.
>
>
> drivers/tty/serial/8250/8250_dw.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/tty/serial/8250/8250_dw.c
> b/drivers/tty/serial/8250/8250_dw.c
> index a3fb95d..47d1f3e 100644
> --- a/drivers/tty/serial/8250/8250_dw.c
> +++ b/drivers/tty/serial/8250/8250_dw.c
> @@ -104,15 +104,16 @@ static void dw8250_check_lcr(struct uart_port
> *p, int value)
> dw8250_force_idle(p);
>
> #ifdef CONFIG_64BIT
> - __raw_writeq(value & 0xff, offset);
> -#else
> + if (p->type == PORT_OCTEON)
> + __raw_writeq(value & 0xff, offset);
> + else
> +#endif
> if (p->iotype == UPIO_MEM32)
> writel(value, offset);
> else if (p->iotype == UPIO_MEM32BE)
> iowrite32be(value, offset);
> else
> writeb(value, offset);
> -#endif
So, this changes logic to write the value on any 64 platform, using
different (non-64-bit) accessors, so, the case to fix is
actually "64BIT && !PORT_OCTEON". Perhaps commit message should be
amended to point that clearly.
> }
> /*
> * FIXME: this deadlocks if port->lock is already held
--
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy
next prev parent reply other threads:[~2016-04-05 10:50 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-05 3:32 [PATCH v3] serial: 8250_dw: fix wrong logic in dw8250_check_lcr() Kefeng Wang
2016-04-05 4:02 ` Greg Kroah-Hartman
2016-04-05 4:55 ` Kefeng Wang
2016-04-05 5:53 ` [PATCH v4] " Kefeng Wang
2016-04-05 10:50 ` Andy Shevchenko [this message]
2016-04-07 8:33 ` Kefeng Wang
2016-04-19 8:29 ` Kefeng Wang
2016-04-29 0:44 ` Greg Kroah-Hartman
2016-05-02 9:19 ` [PATCH v5] " Kefeng Wang
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