From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Bryan O'Donoghue <pure.logic@nexus-software.ie>,
Peter Hurley <peter@hurleysoftware.com>,
linux-serial@vger.kernel.org, Vinod Koul <vinod.koul@intel.com>,
linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
ismo.puustinen@intel.com,
Heikki Krogerus <heikki.krogerus@linux.intel.com>
Subject: Re: [PATCH v4 09/11] serial: 8250_lpss: move Quark code from PCI driver
Date: Wed, 04 May 2016 18:40:18 +0300 [thread overview]
Message-ID: <1462376418.17131.259.camel@linux.intel.com> (raw)
In-Reply-To: <1462374847.27858.205.camel@nexus-software.ie>
On Wed, 2016-05-04 at 16:14 +0100, Bryan O'Donoghue wrote:
> On Wed, 2016-05-04 at 17:32 +0300, Andy Shevchenko wrote:
> >
> > Intel Quark has DesignWare UART. Move the code from 8250_pci to
> > 8250_lpss.
> >
> > Reviewed-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
> > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> > ---
> > drivers/tty/serial/8250/8250_lpss.c | 11 +++++++++++
> > drivers/tty/serial/8250/8250_pci.c | 15 +--------------
> > 2 files changed, 12 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/tty/serial/8250/8250_lpss.c
> > b/drivers/tty/serial/8250/8250_lpss.c
> > index 77cf7e3..3beb3aa 100644
> > --- a/drivers/tty/serial/8250/8250_lpss.c
> > +++ b/drivers/tty/serial/8250/8250_lpss.c
> > @@ -25,6 +25,8 @@
> > #define PCI_DEVICE_ID_INTEL_BSW_UART1 0x228a
> > #define PCI_DEVICE_ID_INTEL_BSW_UART2 0x228c
> >
> > +#define PCI_DEVICE_ID_INTEL_QRK_UARTx 0x0936
> > +
> > #define PCI_DEVICE_ID_INTEL_BDW_UART1 0x9ce3
> > #define PCI_DEVICE_ID_INTEL_BDW_UART2 0x9ce4
> >
> > @@ -165,6 +167,9 @@ static int lpss8250_dma_setup(struct lpss8250
> > *lpss, struct uart_8250_port *port
> > struct dw_dma_slave *rx_param, *tx_param;
> > struct device *dev = port->port.dev;
> >
> > + if (!lpss->dma_param.dma_dev)
> > + return 0;
> > +
> > rx_param = devm_kzalloc(dev, sizeof(*rx_param),
> > GFP_KERNEL);
> > if (!rx_param)
> > return -ENOMEM;
> > @@ -252,6 +257,11 @@ static const struct lpss8250_board byt_board =
> > {
> > .setup = byt_serial_setup,
> > };
> >
> > +static const struct lpss8250_board qrk_board = {
> > + .freq = 44236800,
> > + .base_baud = 2764800,
> > +};
> > +
> > #define LPSS_DEVICE(id, board) { PCI_VDEVICE(INTEL, id),
> > (kernel_ulong_t)&board }
> >
> > static const struct pci_device_id pci_ids[] = {
> > @@ -259,6 +269,7 @@ static const struct pci_device_id pci_ids[] = {
> > LPSS_DEVICE(PCI_DEVICE_ID_INTEL_BYT_UART2, byt_board),
> > LPSS_DEVICE(PCI_DEVICE_ID_INTEL_BSW_UART1, byt_board),
> > LPSS_DEVICE(PCI_DEVICE_ID_INTEL_BSW_UART2, byt_board),
> > + LPSS_DEVICE(PCI_DEVICE_ID_INTEL_QRK_UARTx, qrk_board),
> > LPSS_DEVICE(PCI_DEVICE_ID_INTEL_BDW_UART1, byt_board),
> > LPSS_DEVICE(PCI_DEVICE_ID_INTEL_BDW_UART2, byt_board),
> > { },
> > diff --git a/drivers/tty/serial/8250/8250_pci.c
> > b/drivers/tty/serial/8250/8250_pci.c
> > index bb4df5d..b94b1ee 100644
> > --- a/drivers/tty/serial/8250/8250_pci.c
> > +++ b/drivers/tty/serial/8250/8250_pci.c
> > @@ -1765,7 +1765,6 @@ pci_wch_ch38x_setup(struct serial_private
> > *priv,
> > #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
> > #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
> > #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
> > -#define PCI_DEVICE_ID_INTEL_QRK_UART 0x0936
> >
> > #define PCI_VENDOR_ID_SUNIX 0x1fd4
> > #define PCI_DEVICE_ID_SUNIX_1999 0x1999
> > @@ -2736,7 +2735,6 @@ enum pci_board_num_t {
> > pbn_ADDIDATA_PCIe_4_3906250,
> > pbn_ADDIDATA_PCIe_8_3906250,
> > pbn_ce4100_1_115200,
> > - pbn_qrk,
> > pbn_omegapci,
> > pbn_NETMOS9900_2s_115200,
> > pbn_brcm_trumanage,
> > @@ -3512,12 +3510,6 @@ static struct pciserial_board pci_boards[] =
> > {
> > .base_baud = 921600,
> > .reg_shift = 2,
> > },
> > - [pbn_qrk] = {
> > - .flags = FL_BASE0,
> > - .num_ports = 1,
> > - .base_baud = 2764800,
> > - .reg_shift = 2,
> > - },
> > [pbn_omegapci] = {
> > .flags = FL_BASE0,
> > .num_ports = 8,
> > @@ -3634,6 +3626,7 @@ static const struct pci_device_id blacklist[]
> > =
> > {
> > { PCI_VDEVICE(INTEL, 0x0f0c), },
> > { PCI_VDEVICE(INTEL, 0x228a), },
> > { PCI_VDEVICE(INTEL, 0x228c), },
> > + { PCI_VDEVICE(INTEL, 0x0936), },
> > { PCI_VDEVICE(INTEL, 0x9ce3), },
> > { PCI_VDEVICE(INTEL, 0x9ce4), },
> > };
> > @@ -5303,12 +5296,6 @@ static struct pci_device_id serial_pci_tbl[]
> > =
> > {
> > pbn_ce4100_1_115200 },
> >
> > /*
> > - * Intel Quark x1000
> > - */
> > - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART,
> > - PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> > - pbn_qrk },
> > - /*
> > * Cronyx Omega PCI
> > */
> > { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
> Andy.
>
> Could you please add CONFIG_SERIAL_8250_LPSS when
> CONFIG_X86_INTEL_QUARK is true for my "Reviewed-by" to this patch ?
>
> I don't see that
Wait, what you are proposing here is a new behaviour, right?
Or can you explain how it works now (w/o this series being applied)?
--
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy
next prev parent reply other threads:[~2016-05-04 15:40 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-04 14:32 [PATCH v4 00/11] serial: 8250: split LPSS to 8250_lpss, enable DMA on Quark Andy Shevchenko
2016-05-04 14:32 ` [PATCH v4 01/11] dmaengine: dw: keep copy of custom slave config in dwc Andy Shevchenko
2016-05-04 14:32 ` [PATCH v4 02/11] dmaengine: dw: provide probe(), remove() stubs for users Andy Shevchenko
2016-05-04 14:32 ` [PATCH v4 03/11] dmaengine: dw: set polarity of handshake interface Andy Shevchenko
2016-05-04 14:32 ` [PATCH v4 04/11] dmaengine: dw: override LLP support if asked in platform data Andy Shevchenko
2016-05-04 14:32 ` [PATCH v4 05/11] serial: 8250_dma: switch to new dmaengine_terminate_* API Andy Shevchenko
2016-05-04 14:32 ` [PATCH v4 06/11] serial: 8250_dma: adjust DMA address of the UART Andy Shevchenko
2016-05-04 14:32 ` [PATCH v4 07/11] serial: 8250: enable AFE on ports where FIFO is 16 bytes Andy Shevchenko
2016-05-04 14:32 ` [PATCH v4 08/11] serial: 8250_lpss: split LPSS driver to separate module Andy Shevchenko
2016-05-04 15:10 ` kbuild test robot
2016-05-04 14:32 ` [PATCH v4 09/11] serial: 8250_lpss: move Quark code from PCI driver Andy Shevchenko
2016-05-04 15:14 ` Bryan O'Donoghue
2016-05-04 15:40 ` Andy Shevchenko [this message]
2016-05-04 14:32 ` [PATCH v4 10/11] serial: 8250_lpss: enable MSI for Intel Quark Andy Shevchenko
2016-05-04 14:32 ` [PATCH v4 11/11] serial: 8250_lpss: enable DMA on Intel Quark UART Andy Shevchenko
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1462376418.17131.259.camel@linux.intel.com \
--to=andriy.shevchenko@linux.intel.com \
--cc=dmaengine@vger.kernel.org \
--cc=gregkh@linuxfoundation.org \
--cc=heikki.krogerus@linux.intel.com \
--cc=ismo.puustinen@intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-serial@vger.kernel.org \
--cc=peter@hurleysoftware.com \
--cc=pure.logic@nexus-software.ie \
--cc=vinod.koul@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).