Serial driver related problems on Linux

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* Serial driver related problems on Linux
@ 2005-03-10 15:41 Bob Bell
  2005-03-15  2:11 ` Theodore Ts'o
  0 siblings, 1 reply; 4+ messages in thread
From: Bob Bell @ 2005-03-10 15:41 UTC (permalink / raw)
  To: linux-serial

[-- Attachment #1: Type: text/plain, Size: 2610 bytes --]

Ted, Russell, whomever,

I'm contacting you because I'm experiencing a problem on Linux with a
serial line, and I've traced the problem as far as the Linux kernel.
I'm hoping that this is the best way to further troubleshoot this
problem; I noted that Ted T'so is listed as the maintainer for the 2.4
series (I'm running a 2.4.21 kernel) and Russell for the 2.6 series, so
I'm hoping a message sent to this mailing list gets the attention of
whomever is currently actively maintaining the serial/tty code.

The user-visible symptoms of this problem are that after typing in a
username and hitting enter, the serial login prompt hangs.  I've traced
this hang to an ioctl in the login code (TCSETSF, a result of calling
tcsetattr(,TCSAFLUSH,)).  I've further traced that ioctl to being stuck
in tty_wait_until_sent().

As part of debugging this problem, I've attempted to #define
TTY_DEBUG_WAIT_UNTIL_SENT and SERIAL_DEBUG_RS_WAIT_UNTIL_SENT.  However,
the printk()s that these #defines add make the problem go away.
Similarly, adding any of my own printk()s make the problem go away.
Therefore, I've instead mimicked the printk()s with calls to my own
routine (dbg_addmsg()) to add the same output to an in-kernel buffer.
It's a quick hack, but the problem does indeed persist with this
debugging technique, and it captures what the printk() output, with
which you may be familiar, would have been.  I've attached my changes as
linux.tty_debug.patch; hopefully, they are very straight-forward.

The debugging output has a lot of references to "pts", which is not
surprising as I'm running `crash`, etc. from an ssh login.  Filtering
those out leaves the following from the time of the login:
    ttyS wait until sent...
    waiting ttyS...(1)
    waiting ttyS...(62)
    interrupted

There is a long delay between "(1)" and "(62)".  This delay corresponds
to the amount of time login has set for SIGALRM.  I've bumped this time
from 1 minute to 5 minutes.  After 5 minutes of waiting, the wait is
finally interrupted by the signal, as indicated by the "interrupted"
output line that I added (not in the original debug printk()s).  During
this time, there is no output from rs_wait_until_sent().  I've attached
the output with all "pts" lines filtered out as "output.nonpts".

Do you have any idea what could be going on here?  I've put in notable
time getting this far, and I'm willing to work with whomever to further
debug this problem.  I've also attached the output of `lspci -v` as
'lspci.out', so that you can get an idea as to the type of hardware I'm
dealing with.

Thank you for your time.

    -- Bob

[-- Attachment #2: linux.tty_debug.patch --]
[-- Type: text/plain, Size: 3104 bytes --]

diff -rup --exclude '*SCCS*' --exclude BitKeeper linux.orig/drivers/char/serial.c linux/drivers/char/serial.c
--- linux.orig/drivers/char/serial.c	Wed Mar  9 17:47:18 2005
+++ linux/drivers/char/serial.c	Wed Mar  9 16:40:09 2005
@@ -265,6 +265,9 @@ static int serial_refcount;
 
 static struct timer_list serial_timer;
 
+extern pid_t watched_pid;
+extern void dbg_addmsg(char *fmt, ...);
+
 /* serial subtype definitions */
 #ifndef SERIAL_TYPE_NORMAL
 #define SERIAL_TYPE_NORMAL	1
@@ -2945,10 +2948,13 @@ static void rs_wait_until_sent(struct tt
 	printk("In rs_wait_until_sent(%d) check=%lu...", timeout, char_time);
 	printk("jiff=%lu...", jiffies);
 #endif
+	dbg_addmsg("In rs_wait_until_sent(%d) check=%lu...", timeout, char_time);
+	dbg_addmsg("jiff=%lu...", jiffies);
 	while (!((lsr = serial_inp(info, UART_LSR)) & UART_LSR_TEMT)) {
 #ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
 		printk("lsr = %d (jiff=%lu)...", lsr, jiffies);
 #endif
+		dbg_addmsg("lsr = %d (jiff=%lu)...", lsr, jiffies);
 		set_current_state(TASK_INTERRUPTIBLE);
 		schedule_timeout(char_time);
 		if (signal_pending(current))
@@ -2959,6 +2965,7 @@ static void rs_wait_until_sent(struct tt
 #ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
 	printk("lsr = %d (jiff=%lu)...done\n", lsr, jiffies);
 #endif
+	dbg_addmsg("lsr = %d (jiff=%lu)...done\n", lsr, jiffies);
 }
 
 /*
diff -rup --exclude '*SCCS*' --exclude BitKeeper linux.orig/drivers/char/tty_ioctl.c linux/drivers/char/tty_ioctl.c
--- linux.orig/drivers/char/tty_ioctl.c	Wed Mar  9 17:47:18 2005
+++ linux/drivers/char/tty_ioctl.c	Wed Mar  9 17:15:31 2005
@@ -25,6 +25,16 @@
 #include <asm/uaccess.h>
 #include <asm/system.h>
 
+char dbg_msgbuf[1024*128] = { '\0' };
+char *dbg_msgcur = dbg_msgbuf;
+void dbg_addmsg(char *fmt, ...) {
+    va_list args;
+    va_start(args, fmt);
+    dbg_msgcur += vsprintf(dbg_msgcur, fmt, args);
+    va_end(args);
+}
+
+
 #undef TTY_DEBUG_WAIT_UNTIL_SENT
 
 #undef	DEBUG
@@ -40,11 +50,12 @@ void tty_wait_until_sent(struct tty_stru
 {
 	DECLARE_WAITQUEUE(wait, current);
 
-#ifdef TTY_DEBUG_WAIT_UNTIL_SENT
 	char buf[64];
+#ifdef TTY_DEBUG_WAIT_UNTIL_SENT
 	
 	printk(KERN_DEBUG "%s wait until sent...\n", tty_name(tty, buf));
 #endif
+	dbg_addmsg("%s wait until sent...\n", tty_name(tty, buf));
 	if (!tty->driver.chars_in_buffer)
 		return;
 	add_wait_queue(&tty->write_wait, &wait);
@@ -55,13 +66,19 @@ void tty_wait_until_sent(struct tty_stru
 		printk(KERN_DEBUG "waiting %s...(%d)\n", tty_name(tty, buf),
 		       tty->driver.chars_in_buffer(tty));
 #endif
+		dbg_addmsg("waiting %s...(%d)\n", tty_name(tty, buf),
+			   tty->driver.chars_in_buffer(tty));
 		set_current_state(TASK_INTERRUPTIBLE);
-		if (signal_pending(current))
+		if (signal_pending(current)) {
+			dbg_addmsg("interrupted\n");
 			goto stop_waiting;
+		}
 		if (!tty->driver.chars_in_buffer(tty))
 			break;
 		timeout = schedule_timeout(timeout);
 	} while (timeout);
+	dbg_addmsg("done waiting %s...(%d)\n", tty_name(tty, buf),
+		   tty->driver.chars_in_buffer(tty));
 	if (tty->driver.wait_until_sent)
 		tty->driver.wait_until_sent(tty, timeout);
 stop_waiting:

[-- Attachment #3: output.nonpts --]
[-- Type: text/plain, Size: 1752 bytes --]

ttyS wait until sent...
waiting ttyS...(0)
done waiting ttyS...(0)
In rs_wait_until_sent(6) check=1...jiff=1819...lsr = 96 (jiff=1819)...done
In rs_wait_until_sent(3) check=1...jiff=1819...lsr = 96 (jiff=1819)...done
ttyS wait until sent...
waiting ttyS...(0)
done waiting ttyS...(0)
In rs_wait_until_sent(6) check=1...jiff=1819...lsr = 96 (jiff=1819)...done
ttyS wait until sent...
waiting ttyS...(0)
done waiting ttyS...(0)
In rs_wait_until_sent(6) check=1...jiff=1819...lsr = 96 (jiff=1819)...done
In rs_wait_until_sent(3) check=1...jiff=1819...lsr = 96 (jiff=1819)...done
ttyS wait until sent...
waiting ttyS...(0)
done waiting ttyS...(0)
In rs_wait_until_sent(6) check=1...jiff=1822...lsr = 0 (jiff=1822)...lsr = 96 (jiff=1823)...done
In rs_wait_until_sent(3) check=1...jiff=1823...lsr = 96 (jiff=1823)...done
ttyS wait until sent...
waiting ttyS...(4)
waiting ttyS...(0)
done waiting ttyS...(0)
In rs_wait_until_sent(6) check=1...jiff=1824...lsr = 0 (jiff=1824)...lsr = 0 (jiff=1825)...lsr = 96 (jiff=1826)...done
In rs_wait_until_sent(3) check=1...jiff=1826...lsr = 96 (jiff=1826)...done
ttyS wait until sent...
waiting ttyS...(0)
done waiting ttyS...(0)
In rs_wait_until_sent(6) check=1...jiff=1826...lsr = 0 (jiff=1826)...lsr = 96 (jiff=1827)...done
In rs_wait_until_sent(3) check=1...jiff=1827...lsr = 96 (jiff=1827)...done
ttyS wait until sent...
waiting ttyS...(0)
done waiting ttyS...(0)
In rs_wait_until_sent(6) check=1...jiff=1828...lsr = 96 (jiff=1828)...done
ttyS wait until sent...
waiting ttyS...(0)
done waiting ttyS...(0)
ttyS wait until sent...
waiting ttyS...(0)
done waiting ttyS...(0)
ttyS wait until sent...
waiting ttyS...(0)
done waiting ttyS...(0)
ttyS wait until sent...
waiting ttyS...(1)
waiting ttyS...(62)
interrupted

[-- Attachment #4: lspci.out --]
[-- Type: text/plain, Size: 3884 bytes --]

00:00.0 Host bridge: Intel Corporation: Unknown device 2560 (rev 01)
	Subsystem: Intel Corporation: Unknown device 2560
	Flags: bus master, fast devsel, latency 0
	Memory at e8000000 (32-bit, prefetchable) [size=64M]
	Capabilities: [e4] #09 [1105]

00:02.0 VGA compatible controller: Intel Corporation: Unknown device 2562 (rev 01) (prog-if 00 [VGA])
	Subsystem: Intel Corporation: Unknown device 2562
	Flags: bus master, fast devsel, latency 0, IRQ 10
	Memory at e0000000 (32-bit, prefetchable) [size=128M]
	Memory at ec100000 (32-bit, non-prefetchable) [size=512K]
	Capabilities: [d0] Power Management version 1

00:1d.0 USB Controller: Intel Corporation: Unknown device 24c2 (rev 01) (prog-if 00 [UHCI])
	Subsystem: Intel Corporation: Unknown device 24c2
	Flags: bus master, medium devsel, latency 0, IRQ 10
	I/O ports at d800 [size=32]

00:1d.1 USB Controller: Intel Corporation: Unknown device 24c4 (rev 01) (prog-if 00 [UHCI])
	Subsystem: Intel Corporation: Unknown device 24c2
	Flags: bus master, medium devsel, latency 0, IRQ 3
	I/O ports at d000 [size=32]

00:1d.2 USB Controller: Intel Corporation: Unknown device 24c7 (rev 01) (prog-if 00 [UHCI])
	Subsystem: Intel Corporation: Unknown device 24c2
	Flags: bus master, medium devsel, latency 0, IRQ 7
	I/O ports at d400 [size=32]

00:1d.7 USB Controller: Intel Corporation: Unknown device 24cd (rev 01) (prog-if 20)
	Subsystem: Intel Corporation: Unknown device 24cd
	Flags: bus master, medium devsel, latency 0, IRQ 5
	Memory at ec180000 (32-bit, non-prefetchable) [size=1K]
	Capabilities: [50] Power Management version 2

00:1e.0 PCI bridge: Intel Corporation 82820 820 (Camino 2) Chipset PCI (rev 81) (prog-if 00 [Normal decode])
	Flags: bus master, fast devsel, latency 0
	Bus: primary=00, secondary=01, subordinate=01, sec-latency=32
	I/O behind bridge: 0000c000-0000cfff
	Memory behind bridge: ec000000-ec0fffff

00:1f.0 ISA bridge: Intel Corporation: Unknown device 24c0 (rev 01)
	Flags: bus master, medium devsel, latency 0

00:1f.1 IDE interface: Intel Corporation: Unknown device 24cb (rev 01) (prog-if 8a [Master SecP PriP])
	Subsystem: Intel Corporation: Unknown device 24c2
	Flags: bus master, medium devsel, latency 0, IRQ 10
	I/O ports at <unassigned>
	I/O ports at <unassigned>
	I/O ports at <unassigned>
	I/O ports at <unassigned>
	I/O ports at f000 [size=16]
	Memory at 7f800000 (32-bit, non-prefetchable) [size=1K]

00:1f.3 SMBus: Intel Corporation: Unknown device 24c3 (rev 01)
	Subsystem: Intel Corporation: Unknown device 24c2
	Flags: medium devsel, IRQ 9
	I/O ports at 0500 [size=32]

01:03.0 Ethernet controller: Intel Corporation 82557 [Ethernet Pro 100] (rev 10)
	Subsystem: Intel Corporation: Unknown device 1040
	Flags: bus master, medium devsel, latency 32, IRQ 12
	Memory at ec0a1000 (32-bit, non-prefetchable) [size=4K]
	I/O ports at c000 [size=64]
	Memory at ec000000 (32-bit, non-prefetchable) [size=128K]
	Capabilities: [dc] Power Management version 2

01:04.0 Ethernet controller: Intel Corporation: Unknown device 100e (rev 02)
	Subsystem: Intel Corporation: Unknown device 002e
	Flags: bus master, 66Mhz, medium devsel, latency 32, IRQ 10
	Memory at ec020000 (32-bit, non-prefetchable) [size=128K]
	Memory at ec040000 (32-bit, non-prefetchable) [size=128K]
	I/O ports at c400 [size=64]
	Expansion ROM at <unassigned> [disabled] [size=128K]
	Capabilities: [dc] Power Management version 2
	Capabilities: [e4] PCI-X non-bridge device.
	Capabilities: [f0] Message Signalled Interrupts: 64bit+ Queue=0/0 Enable-

01:06.0 Ethernet controller: Intel Corporation 82557 [Ethernet Pro 100] (rev 10)
	Subsystem: Intel Corporation: Unknown device 1040
	Flags: bus master, medium devsel, latency 32, IRQ 11
	Memory at ec0a0000 (32-bit, non-prefetchable) [size=4K]
	I/O ports at c800 [size=64]
	Memory at ec080000 (32-bit, non-prefetchable) [size=128K]
	Capabilities: [dc] Power Management version 2


^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: Serial driver related problems on Linux
  2005-03-10 15:41 Serial driver related problems on Linux Bob Bell
@ 2005-03-15  2:11 ` Theodore Ts'o
  2005-03-17 18:07   ` Bob Bell
  0 siblings, 1 reply; 4+ messages in thread
From: Theodore Ts'o @ 2005-03-15  2:11 UTC (permalink / raw)
  To: Bob Bell; +Cc: linux-serial

On Thu, Mar 10, 2005 at 10:41:27AM -0500, Bob Bell wrote:
> 
> I'm contacting you because I'm experiencing a problem on Linux with a
> serial line, and I've traced the problem as far as the Linux kernel.
> I'm hoping that this is the best way to further troubleshoot this
> problem; I noted that Ted T'so is listed as the maintainer for the 2.4
> series (I'm running a 2.4.21 kernel) and Russell for the 2.6 series, so
> I'm hoping a message sent to this mailing list gets the attention of
> whomever is currently actively maintaining the serial/tty code.
> 
> The user-visible symptoms of this problem are that after typing in a
> username and hitting enter, the serial login prompt hangs.  I've traced
> this hang to an ioctl in the login code (TCSETSF, a result of calling
> tcsetattr(,TCSAFLUSH,)).  I've further traced that ioctl to being stuck
> in tty_wait_until_sent().
> 
> The debugging output has a lot of references to "pts", which is not
> surprising as I'm running `crash`, etc. from an ssh login.  Filtering
> those out leaves the following from the time of the login:
>     ttyS wait until sent...
>     waiting ttyS...(1)
>     waiting ttyS...(62)
>     interrupted

It's possible this was caused by a lost transmitter interrupt, so the
transmit queue never drained; it's also possible that some UART's are
wired to not signal a transmitter interrupt while the serial port is
flow controlled.  In order to figure out what is going on, you'd have
to add debugging logic into the interrupt handler as well (i.e.,
#define SERIAL_DEBUG_INTR).

						- Ted

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: Serial driver related problems on Linux
  2005-03-15  2:11 ` Theodore Ts'o
@ 2005-03-17 18:07   ` Bob Bell
  2005-03-30 12:49     ` Bob Bell
  0 siblings, 1 reply; 4+ messages in thread
From: Bob Bell @ 2005-03-17 18:07 UTC (permalink / raw)
  To: Theodore Ts'o; +Cc: linux-serial

[-- Attachment #1: Type: text/plain, Size: 1896 bytes --]

On Mon, Mar 14, 2005 at 09:11:28PM -0500, Theodore Ts'o <tytso@mit.edu> wrote:
> On Thu, Mar 10, 2005 at 10:41:27AM -0500, Bob Bell wrote:
> > The user-visible symptoms of this problem are that after typing in a
> > username and hitting enter, the serial login prompt hangs.  I've traced
> > this hang to an ioctl in the login code (TCSETSF, a result of calling
> > tcsetattr(,TCSAFLUSH,)).  I've further traced that ioctl to being stuck
> > in tty_wait_until_sent().
> 
> It's possible this was caused by a lost transmitter interrupt, so the
> transmit queue never drained; it's also possible that some UART's are
> wired to not signal a transmitter interrupt while the serial port is
> flow controlled.  In order to figure out what is going on, you'd have
> to add debugging logic into the interrupt handler as well (i.e.,
> #define SERIAL_DEBUG_INTR).

I've #defined SERIAL_DEBUG_INTR as you indicated.  In order to minimize
the impact that might cause, I also #defined printk() to be equivalent
to my debugging routine, dbg_addmsg().  The following was captured
starting after I typing in my username, but before I hit enter:
    rs_interrupt_single(4)...status = 61...DR0d:61...IIR = c1...end.
    rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
    <7>ttyS wait until sent...
    <7>waiting ttyS...(1)
    rs_interrupt_single(4)...status = 0...IIR = c1...end.
    [ the preceding line repeats another 28x, about once every 10 seconds ]
    <7>waiting ttyS...(62)
    <7>waiting on ttyS interrupted

I've attached a complete log, starting at boot time, as
log_complete.out.  I've also attached my updated patch to the Linux
kernel that I used to capture the debugging output, just for
completeness.

Thanks for the guidance.  I'm not sure what this output demonstrates,
but I hope it gets us at least one step closer to the cause...

-- 
Bob Bell <bbell@users.sourceforge.net>

[-- Attachment #2: log_complete.out --]
[-- Type: text/plain, Size: 34293 bytes --]

<6>Serial driver version 5.05c (2001-07-08) with MANY_PORTS SHARE_IRQ SERIAL_PCI enabled
<6>ttyS00 at 0x03f8 (irq = 4) is a 16550A
<7>ttyS wait until sent...
<7>waiting ttyS...(0)
done waiting ttyS...(0)
In rs_wait_until_sent(6) check=1...jiff=1799...lsr = 96 (jiff=1799)...done
In rs_wait_until_sent(3) check=1...jiff=1799...lsr = 96 (jiff=1799)...done
<7>ttyS wait until sent...
<7>waiting ttyS...(0)
done waiting ttyS...(0)
In rs_wait_until_sent(6) check=1...jiff=1799...lsr = 96 (jiff=1799)...done
<7>ttyS wait until sent...
<7>waiting ttyS...(0)
done waiting ttyS...(0)
In rs_wait_until_sent(6) check=1...jiff=1799...lsr = 96 (jiff=1799)...done
In rs_wait_until_sent(3) check=1...jiff=1799...lsr = 96 (jiff=1799)...done
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
<7>ttyS wait until sent...
<7>waiting ttyS...(0)
done waiting ttyS...(0)
In rs_wait_until_sent(6) check=1...jiff=1802...lsr = 0 (jiff=1802)...lsr = 96 (jiff=1803)...done
In rs_wait_until_sent(3) check=1...jiff=1803...lsr = 96 (jiff=1803)...done
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
<7>ttyS wait until sent...
<7>waiting ttyS...(4)
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
<7>waiting ttyS...(0)
done waiting ttyS...(0)
In rs_wait_until_sent(6) check=1...jiff=1804...lsr = 0 (jiff=1804)...lsr = 0 (jiff=1805)...lsr = 96 (jiff=1806)...done
In rs_wait_until_sent(3) check=1...jiff=1806...lsr = 96 (jiff=1806)...done
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
<7>ttyS wait until sent...
<7>waiting ttyS...(0)
done waiting ttyS...(0)
In rs_wait_until_sent(6) check=1...jiff=1806...lsr = 0 (jiff=1806)...lsr = 96 (jiff=1807)...done
In rs_wait_until_sent(3) check=1...jiff=1807...lsr = 96 (jiff=1807)...done
<7>ttyS wait until sent...
<7>waiting ttyS...(0)
done waiting ttyS...(0)
In rs_wait_until_sent(6) check=1...jiff=1809...lsr = 96 (jiff=1809)...done
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
<7>ttyS wait until sent...
<7>waiting ttyS...(0)
done waiting ttyS...(0)
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
<7>ttyS wait until sent...
<7>waiting ttyS...(0)
done waiting ttyS...(0)
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
<7>ttyS wait until sent...
<7>waiting ttyS...(0)
done waiting ttyS...(0)
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 61...DR0d:61...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 61...DR72:61...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 61...DR6f:61...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 61...DR6f:61...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 61...DR74:61...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
rs_interrupt_single(4)...status = 60...IIR = c1...end.
rs_interrupt_single(4)...status = 61...DR0d:61...IIR = c1...end.
rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
<7>ttyS wait until sent...
<7>waiting ttyS...(1)
rs_interrupt_single(4)...status = 0...IIR = c1...end.
rs_interrupt_single(4)...status = 0...IIR = c1...end.
rs_interrupt_single(4)...status = 0...IIR = c1...end.
rs_interrupt_single(4)...status = 0...IIR = c1...end.
rs_interrupt_single(4)...status = 0...IIR = c1...end.
rs_interrupt_single(4)...status = 0...IIR = c1...end.
rs_interrupt_single(4)...status = 0...IIR = c1...end.
rs_interrupt_single(4)...status = 0...IIR = c1...end.
rs_interrupt_single(4)...status = 0...IIR = c1...end.
rs_interrupt_single(4)...status = 0...IIR = c1...end.
rs_interrupt_single(4)...status = 0...IIR = c1...end.
rs_interrupt_single(4)...status = 0...IIR = c1...end.
rs_interrupt_single(4)...status = 0...IIR = c1...end.
rs_interrupt_single(4)...status = 0...IIR = c1...end.
rs_interrupt_single(4)...status = 0...IIR = c1...end.
rs_interrupt_single(4)...status = 0...IIR = c1...end.
rs_interrupt_single(4)...status = 0...IIR = c1...end.
rs_interrupt_single(4)...status = 0...IIR = c1...end.
rs_interrupt_single(4)...status = 0...IIR = c1...end.
rs_interrupt_single(4)...status = 0...IIR = c1...end.
rs_interrupt_single(4)...status = 0...IIR = c1...end.
rs_interrupt_single(4)...status = 0...IIR = c1...end.
rs_interrupt_single(4)...status = 0...IIR = c1...end.
rs_interrupt_single(4)...status = 0...IIR = c1...end.
rs_interrupt_single(4)...status = 0...IIR = c1...end.
rs_interrupt_single(4)...status = 0...IIR = c1...end.
rs_interrupt_single(4)...status = 0...IIR = c1...end.
rs_interrupt_single(4)...status = 0...IIR = c1...end.
rs_interrupt_single(4)...status = 0...IIR = c1...end.
rs_interrupt_single(4)...status = 0...IIR = c1...end.
<7>waiting ttyS...(62)
<7>waiting on ttyS interrupted

[-- Attachment #3: linux.tty_debug.2.patch --]
[-- Type: text/plain, Size: 4411 bytes --]

diff -rup --exclude '*SCCS*' --exclude BitKeeper linux.orig/drivers/char/serial.c linux/drivers/char/serial.c
--- linux.orig/drivers/char/serial.c	Wed Mar  9 17:47:18 2005
+++ linux/drivers/char/serial.c	Thu Mar 17 12:04:54 2005
@@ -140,10 +140,10 @@ static char *serial_revdate = "2001-07-0
 
 /* Set of debugging defines */
 
-#undef SERIAL_DEBUG_INTR
+#define SERIAL_DEBUG_INTR
 #undef SERIAL_DEBUG_OPEN
 #undef SERIAL_DEBUG_FLOW
-#undef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
+#define SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
 #undef SERIAL_DEBUG_PCI
 #undef SERIAL_DEBUG_AUTOCONF
 
@@ -265,6 +265,10 @@ static int serial_refcount;
 
 static struct timer_list serial_timer;
 
+extern pid_t watched_pid;
+extern void dbg_addmsg(char *fmt, ...);
+#define printk(...) dbg_addmsg(__VA_ARGS__)
+
 /* serial subtype definitions */
 #ifndef SERIAL_TYPE_NORMAL
 #define SERIAL_TYPE_NORMAL	1
@@ -927,7 +931,7 @@ static void rs_interrupt_single(int irq,
 		    ((iir & UART_IIR_ID) == UART_IIR_THRI))
 			transmit_chars(info, 0);
 		if (pass_counter++ > RS_ISR_PASS_LIMIT) {
-#if SERIAL_DEBUG_INTR
+#ifdef SERIAL_DEBUG_INTR
 			printk("rs_single loop break.\n");
 #endif
 			break;
@@ -2942,12 +2946,12 @@ static void rs_wait_until_sent(struct tt
 	if (!timeout || timeout > 2*info->timeout)
 		timeout = 2*info->timeout;
 #ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
-	printk("In rs_wait_until_sent(%d) check=%lu...", timeout, char_time);
-	printk("jiff=%lu...", jiffies);
+	if (tty->driver.type != TTY_DRIVER_TYPE_PTY) printk("In rs_wait_until_sent(%d) check=%lu...", timeout, char_time);
+	if (tty->driver.type != TTY_DRIVER_TYPE_PTY) printk("jiff=%lu...", jiffies);
 #endif
 	while (!((lsr = serial_inp(info, UART_LSR)) & UART_LSR_TEMT)) {
 #ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
-		printk("lsr = %d (jiff=%lu)...", lsr, jiffies);
+		if (tty->driver.type != TTY_DRIVER_TYPE_PTY) printk("lsr = %d (jiff=%lu)...", lsr, jiffies);
 #endif
 		set_current_state(TASK_INTERRUPTIBLE);
 		schedule_timeout(char_time);
@@ -2957,7 +2961,7 @@ static void rs_wait_until_sent(struct tt
 			break;
 	}
 #ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
-	printk("lsr = %d (jiff=%lu)...done\n", lsr, jiffies);
+	if (tty->driver.type != TTY_DRIVER_TYPE_PTY) printk("lsr = %d (jiff=%lu)...done\n", lsr, jiffies);
 #endif
 }
 
diff -rup --exclude '*SCCS*' --exclude BitKeeper linux.orig/drivers/char/tty_ioctl.c linux/drivers/char/tty_ioctl.c
--- linux.orig/drivers/char/tty_ioctl.c	Wed Mar  9 17:47:18 2005
+++ linux/drivers/char/tty_ioctl.c	Thu Mar 17 12:04:56 2005
@@ -25,7 +25,21 @@
 #include <asm/uaccess.h>
 #include <asm/system.h>
 
-#undef TTY_DEBUG_WAIT_UNTIL_SENT
+char dbg_msgbuf[1024*256] = { '\0' };
+char *dbg_msgcur = dbg_msgbuf;
+void dbg_addmsg(char *fmt, ...) {
+    va_list args;
+    va_start(args, fmt);
+    dbg_msgcur += vsprintf(dbg_msgcur, fmt, args);
+    va_end(args);
+    if (dbg_msgcur >= (dbg_msgbuf + sizeof(dbg_msgbuf))) {
+	panic("debug message buffer overflow");
+    }
+}
+
+
+#define TTY_DEBUG_WAIT_UNTIL_SENT
+#define printk(...) dbg_addmsg(__VA_ARGS__)
 
 #undef	DEBUG
 
@@ -43,7 +57,7 @@ void tty_wait_until_sent(struct tty_stru
 #ifdef TTY_DEBUG_WAIT_UNTIL_SENT
 	char buf[64];
 	
-	printk(KERN_DEBUG "%s wait until sent...\n", tty_name(tty, buf));
+	if (tty->driver.type != TTY_DRIVER_TYPE_PTY) printk(KERN_DEBUG "%s wait until sent...\n", tty_name(tty, buf));
 #endif
 	if (!tty->driver.chars_in_buffer)
 		return;
@@ -52,16 +66,21 @@ void tty_wait_until_sent(struct tty_stru
 		timeout = MAX_SCHEDULE_TIMEOUT;
 	do {
 #ifdef TTY_DEBUG_WAIT_UNTIL_SENT
-		printk(KERN_DEBUG "waiting %s...(%d)\n", tty_name(tty, buf),
+		if (tty->driver.type != TTY_DRIVER_TYPE_PTY) printk(KERN_DEBUG "waiting %s...(%d)\n", tty_name(tty, buf),
 		       tty->driver.chars_in_buffer(tty));
 #endif
 		set_current_state(TASK_INTERRUPTIBLE);
-		if (signal_pending(current))
+		if (signal_pending(current)) {
+			if (tty->driver.type != TTY_DRIVER_TYPE_PTY) printk(KERN_DEBUG "waiting on %s interrupted\n", tty_name(tty, buf));
 			goto stop_waiting;
+		}
 		if (!tty->driver.chars_in_buffer(tty))
 			break;
 		timeout = schedule_timeout(timeout);
 	} while (timeout);
+#ifdef TTY_DEBUG_WAIT_UNTIL_SENT
+	if (tty->driver.type != TTY_DRIVER_TYPE_PTY) printk("done waiting %s...(%d)\n", tty_name(tty, buf), tty->driver.chars_in_buffer(tty));
+#endif
 	if (tty->driver.wait_until_sent)
 		tty->driver.wait_until_sent(tty, timeout);
 stop_waiting:

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: Serial driver related problems on Linux
  2005-03-17 18:07   ` Bob Bell
@ 2005-03-30 12:49     ` Bob Bell
  0 siblings, 0 replies; 4+ messages in thread
From: Bob Bell @ 2005-03-30 12:49 UTC (permalink / raw)
  To: Theodore Ts'o; +Cc: linux-serial

I don't recall seeing a reply to my email below (note that I'm not
subscribed to linux-serial, so if the reply went only to the list,
I missed it).  Is there more information that I can provide?  I don't
know how to interpret the output from SERIAL_DEBUG_INTR.

On Thu, Mar 17, 2005 at 01:07:03PM -0500, Bob Bell <bbell@users.sourceforge.net> wrote:
> On Mon, Mar 14, 2005 at 09:11:28PM -0500, Theodore Ts'o <tytso@mit.edu> wrote:
> > On Thu, Mar 10, 2005 at 10:41:27AM -0500, Bob Bell wrote:
> > > The user-visible symptoms of this problem are that after typing in a
> > > username and hitting enter, the serial login prompt hangs.  I've traced
> > > this hang to an ioctl in the login code (TCSETSF, a result of calling
> > > tcsetattr(,TCSAFLUSH,)).  I've further traced that ioctl to being stuck
> > > in tty_wait_until_sent().
> > 
> > It's possible this was caused by a lost transmitter interrupt, so the
> > transmit queue never drained; it's also possible that some UART's are
> > wired to not signal a transmitter interrupt while the serial port is
> > flow controlled.  In order to figure out what is going on, you'd have
> > to add debugging logic into the interrupt handler as well (i.e.,
> > #define SERIAL_DEBUG_INTR).
> 
> I've #defined SERIAL_DEBUG_INTR as you indicated.  In order to minimize
> the impact that might cause, I also #defined printk() to be equivalent
> to my debugging routine, dbg_addmsg().  The following was captured
> starting after I typing in my username, but before I hit enter:
>     rs_interrupt_single(4)...status = 61...DR0d:61...IIR = c1...end.
>     rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
>     <7>ttyS wait until sent...
>     <7>waiting ttyS...(1)
>     rs_interrupt_single(4)...status = 0...IIR = c1...end.
>     [ the preceding line repeats another 28x, about once every 10 seconds ]
>     <7>waiting ttyS...(62)
>     <7>waiting on ttyS interrupted
> 
> I've attached a complete log, starting at boot time, as
> log_complete.out.  I've also attached my updated patch to the Linux
> kernel that I used to capture the debugging output, just for
> completeness.
> 
> Thanks for the guidance.  I'm not sure what this output demonstrates,
> but I hope it gets us at least one step closer to the cause...
> 
> -- 
> Bob Bell <bbell@users.sourceforge.net>

> <6>Serial driver version 5.05c (2001-07-08) with MANY_PORTS SHARE_IRQ SERIAL_PCI enabled
> <6>ttyS00 at 0x03f8 (irq = 4) is a 16550A
> <7>ttyS wait until sent...
> <7>waiting ttyS...(0)
> done waiting ttyS...(0)
> In rs_wait_until_sent(6) check=1...jiff=1799...lsr = 96 (jiff=1799)...done
> In rs_wait_until_sent(3) check=1...jiff=1799...lsr = 96 (jiff=1799)...done
> <7>ttyS wait until sent...
> <7>waiting ttyS...(0)
> done waiting ttyS...(0)
> In rs_wait_until_sent(6) check=1...jiff=1799...lsr = 96 (jiff=1799)...done
> <7>ttyS wait until sent...
> <7>waiting ttyS...(0)
> done waiting ttyS...(0)
> In rs_wait_until_sent(6) check=1...jiff=1799...lsr = 96 (jiff=1799)...done
> In rs_wait_until_sent(3) check=1...jiff=1799...lsr = 96 (jiff=1799)...done
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> <7>ttyS wait until sent...
> <7>waiting ttyS...(0)
> done waiting ttyS...(0)
> In rs_wait_until_sent(6) check=1...jiff=1802...lsr = 0 (jiff=1802)...lsr = 96 (jiff=1803)...done
> In rs_wait_until_sent(3) check=1...jiff=1803...lsr = 96 (jiff=1803)...done
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> <7>ttyS wait until sent...
> <7>waiting ttyS...(4)
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> <7>waiting ttyS...(0)
> done waiting ttyS...(0)
> In rs_wait_until_sent(6) check=1...jiff=1804...lsr = 0 (jiff=1804)...lsr = 0 (jiff=1805)...lsr = 96 (jiff=1806)...done
> In rs_wait_until_sent(3) check=1...jiff=1806...lsr = 96 (jiff=1806)...done
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> <7>ttyS wait until sent...
> <7>waiting ttyS...(0)
> done waiting ttyS...(0)
> In rs_wait_until_sent(6) check=1...jiff=1806...lsr = 0 (jiff=1806)...lsr = 96 (jiff=1807)...done
> In rs_wait_until_sent(3) check=1...jiff=1807...lsr = 96 (jiff=1807)...done
> <7>ttyS wait until sent...
> <7>waiting ttyS...(0)
> done waiting ttyS...(0)
> In rs_wait_until_sent(6) check=1...jiff=1809...lsr = 96 (jiff=1809)...done
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> <7>ttyS wait until sent...
> <7>waiting ttyS...(0)
> done waiting ttyS...(0)
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> <7>ttyS wait until sent...
> <7>waiting ttyS...(0)
> done waiting ttyS...(0)
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> <7>ttyS wait until sent...
> <7>waiting ttyS...(0)
> done waiting ttyS...(0)
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 61...DR0d:61...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 20...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 61...DR72:61...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 61...DR6f:61...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 61...DR6f:61...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 61...DR74:61...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...IIR = c1...end.
> rs_interrupt_single(4)...status = 61...DR0d:61...IIR = c1...end.
> rs_interrupt_single(4)...status = 60...THRE...IIR = c1...end.
> <7>ttyS wait until sent...
> <7>waiting ttyS...(1)
> rs_interrupt_single(4)...status = 0...IIR = c1...end.
> rs_interrupt_single(4)...status = 0...IIR = c1...end.
> rs_interrupt_single(4)...status = 0...IIR = c1...end.
> rs_interrupt_single(4)...status = 0...IIR = c1...end.
> rs_interrupt_single(4)...status = 0...IIR = c1...end.
> rs_interrupt_single(4)...status = 0...IIR = c1...end.
> rs_interrupt_single(4)...status = 0...IIR = c1...end.
> rs_interrupt_single(4)...status = 0...IIR = c1...end.
> rs_interrupt_single(4)...status = 0...IIR = c1...end.
> rs_interrupt_single(4)...status = 0...IIR = c1...end.
> rs_interrupt_single(4)...status = 0...IIR = c1...end.
> rs_interrupt_single(4)...status = 0...IIR = c1...end.
> rs_interrupt_single(4)...status = 0...IIR = c1...end.
> rs_interrupt_single(4)...status = 0...IIR = c1...end.
> rs_interrupt_single(4)...status = 0...IIR = c1...end.
> rs_interrupt_single(4)...status = 0...IIR = c1...end.
> rs_interrupt_single(4)...status = 0...IIR = c1...end.
> rs_interrupt_single(4)...status = 0...IIR = c1...end.
> rs_interrupt_single(4)...status = 0...IIR = c1...end.
> rs_interrupt_single(4)...status = 0...IIR = c1...end.
> rs_interrupt_single(4)...status = 0...IIR = c1...end.
> rs_interrupt_single(4)...status = 0...IIR = c1...end.
> rs_interrupt_single(4)...status = 0...IIR = c1...end.
> rs_interrupt_single(4)...status = 0...IIR = c1...end.
> rs_interrupt_single(4)...status = 0...IIR = c1...end.
> rs_interrupt_single(4)...status = 0...IIR = c1...end.
> rs_interrupt_single(4)...status = 0...IIR = c1...end.
> rs_interrupt_single(4)...status = 0...IIR = c1...end.
> rs_interrupt_single(4)...status = 0...IIR = c1...end.
> rs_interrupt_single(4)...status = 0...IIR = c1...end.
> <7>waiting ttyS...(62)
> <7>waiting on ttyS interrupted

> diff -rup --exclude '*SCCS*' --exclude BitKeeper linux.orig/drivers/char/serial.c linux/drivers/char/serial.c
> --- linux.orig/drivers/char/serial.c	Wed Mar  9 17:47:18 2005
> +++ linux/drivers/char/serial.c	Thu Mar 17 12:04:54 2005
> @@ -140,10 +140,10 @@ static char *serial_revdate = "2001-07-0
>  
>  /* Set of debugging defines */
>  
> -#undef SERIAL_DEBUG_INTR
> +#define SERIAL_DEBUG_INTR
>  #undef SERIAL_DEBUG_OPEN
>  #undef SERIAL_DEBUG_FLOW
> -#undef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
> +#define SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
>  #undef SERIAL_DEBUG_PCI
>  #undef SERIAL_DEBUG_AUTOCONF
>  
> @@ -265,6 +265,10 @@ static int serial_refcount;
>  
>  static struct timer_list serial_timer;
>  
> +extern pid_t watched_pid;
> +extern void dbg_addmsg(char *fmt, ...);
> +#define printk(...) dbg_addmsg(__VA_ARGS__)
> +
>  /* serial subtype definitions */
>  #ifndef SERIAL_TYPE_NORMAL
>  #define SERIAL_TYPE_NORMAL	1
> @@ -927,7 +931,7 @@ static void rs_interrupt_single(int irq,
>  		    ((iir & UART_IIR_ID) == UART_IIR_THRI))
>  			transmit_chars(info, 0);
>  		if (pass_counter++ > RS_ISR_PASS_LIMIT) {
> -#if SERIAL_DEBUG_INTR
> +#ifdef SERIAL_DEBUG_INTR
>  			printk("rs_single loop break.\n");
>  #endif
>  			break;
> @@ -2942,12 +2946,12 @@ static void rs_wait_until_sent(struct tt
>  	if (!timeout || timeout > 2*info->timeout)
>  		timeout = 2*info->timeout;
>  #ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
> -	printk("In rs_wait_until_sent(%d) check=%lu...", timeout, char_time);
> -	printk("jiff=%lu...", jiffies);
> +	if (tty->driver.type != TTY_DRIVER_TYPE_PTY) printk("In rs_wait_until_sent(%d) check=%lu...", timeout, char_time);
> +	if (tty->driver.type != TTY_DRIVER_TYPE_PTY) printk("jiff=%lu...", jiffies);
>  #endif
>  	while (!((lsr = serial_inp(info, UART_LSR)) & UART_LSR_TEMT)) {
>  #ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
> -		printk("lsr = %d (jiff=%lu)...", lsr, jiffies);
> +		if (tty->driver.type != TTY_DRIVER_TYPE_PTY) printk("lsr = %d (jiff=%lu)...", lsr, jiffies);
>  #endif
>  		set_current_state(TASK_INTERRUPTIBLE);
>  		schedule_timeout(char_time);
> @@ -2957,7 +2961,7 @@ static void rs_wait_until_sent(struct tt
>  			break;
>  	}
>  #ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
> -	printk("lsr = %d (jiff=%lu)...done\n", lsr, jiffies);
> +	if (tty->driver.type != TTY_DRIVER_TYPE_PTY) printk("lsr = %d (jiff=%lu)...done\n", lsr, jiffies);
>  #endif
>  }
>  
> diff -rup --exclude '*SCCS*' --exclude BitKeeper linux.orig/drivers/char/tty_ioctl.c linux/drivers/char/tty_ioctl.c
> --- linux.orig/drivers/char/tty_ioctl.c	Wed Mar  9 17:47:18 2005
> +++ linux/drivers/char/tty_ioctl.c	Thu Mar 17 12:04:56 2005
> @@ -25,7 +25,21 @@
>  #include <asm/uaccess.h>
>  #include <asm/system.h>
>  
> -#undef TTY_DEBUG_WAIT_UNTIL_SENT
> +char dbg_msgbuf[1024*256] = { '\0' };
> +char *dbg_msgcur = dbg_msgbuf;
> +void dbg_addmsg(char *fmt, ...) {
> +    va_list args;
> +    va_start(args, fmt);
> +    dbg_msgcur += vsprintf(dbg_msgcur, fmt, args);
> +    va_end(args);
> +    if (dbg_msgcur >= (dbg_msgbuf + sizeof(dbg_msgbuf))) {
> +	panic("debug message buffer overflow");
> +    }
> +}
> +
> +
> +#define TTY_DEBUG_WAIT_UNTIL_SENT
> +#define printk(...) dbg_addmsg(__VA_ARGS__)
>  
>  #undef	DEBUG
>  
> @@ -43,7 +57,7 @@ void tty_wait_until_sent(struct tty_stru
>  #ifdef TTY_DEBUG_WAIT_UNTIL_SENT
>  	char buf[64];
>  	
> -	printk(KERN_DEBUG "%s wait until sent...\n", tty_name(tty, buf));
> +	if (tty->driver.type != TTY_DRIVER_TYPE_PTY) printk(KERN_DEBUG "%s wait until sent...\n", tty_name(tty, buf));
>  #endif
>  	if (!tty->driver.chars_in_buffer)
>  		return;
> @@ -52,16 +66,21 @@ void tty_wait_until_sent(struct tty_stru
>  		timeout = MAX_SCHEDULE_TIMEOUT;
>  	do {
>  #ifdef TTY_DEBUG_WAIT_UNTIL_SENT
> -		printk(KERN_DEBUG "waiting %s...(%d)\n", tty_name(tty, buf),
> +		if (tty->driver.type != TTY_DRIVER_TYPE_PTY) printk(KERN_DEBUG "waiting %s...(%d)\n", tty_name(tty, buf),
>  		       tty->driver.chars_in_buffer(tty));
>  #endif
>  		set_current_state(TASK_INTERRUPTIBLE);
> -		if (signal_pending(current))
> +		if (signal_pending(current)) {
> +			if (tty->driver.type != TTY_DRIVER_TYPE_PTY) printk(KERN_DEBUG "waiting on %s interrupted\n", tty_name(tty, buf));
>  			goto stop_waiting;
> +		}
>  		if (!tty->driver.chars_in_buffer(tty))
>  			break;
>  		timeout = schedule_timeout(timeout);
>  	} while (timeout);
> +#ifdef TTY_DEBUG_WAIT_UNTIL_SENT
> +	if (tty->driver.type != TTY_DRIVER_TYPE_PTY) printk("done waiting %s...(%d)\n", tty_name(tty, buf), tty->driver.chars_in_buffer(tty));
> +#endif
>  	if (tty->driver.wait_until_sent)
>  		tty->driver.wait_until_sent(tty, timeout);
>  stop_waiting:

-- 
Bob Bell <bbell@users.sourceforge.net>

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2005-03-30 12:49 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2005-03-10 15:41 Serial driver related problems on Linux Bob Bell
2005-03-15  2:11 ` Theodore Ts'o
2005-03-17 18:07   ` Bob Bell
2005-03-30 12:49     ` Bob Bell

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