Hardware flowcontrol on XR17D154

Hardware flowcontrol on XR17D154

[Søren holm]

[-- Attachment #1: Type: text/plain, Size: 258 bytes --]

Hi

I have hacked hardware flowcontrol into 8250.c for the XR17D154. I have 
attached the patch. The fix just uses another address for the EFR-register.

I would like to have some adwise as to how to do this the right way. 

Thanks.
-- 
Søren Holm

[-- Attachment #2: xr17d154_hwflow.patch --]
[-- Type: text/x-patch, Size: 1245 bytes --]

diff --git a/drivers/tty/serial/8250.c b/drivers/tty/serial/8250.c
index b3b881b..ba28eb8 100644
--- a/drivers/tty/serial/8250.c
+++ b/drivers/tty/serial/8250.c
@@ -301,7 +301,7 @@ static const struct serial8250_config uart_config[] = {
 		.fifo_size	= 64,
 		.tx_loadsz	= 64,
 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
-		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
+		.flags		= UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR,
 	},
 };
 
@@ -2420,7 +2420,7 @@ serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
 			efr |= UART_EFR_CTS;
 
 		serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
-		serial_outp(up, UART_EFR, efr);
+		serial_outp(up, UART_EFR2, efr);
 	}
 
 #ifdef CONFIG_ARCH_OMAP
diff --git a/include/linux/serial_reg.h b/include/linux/serial_reg.h
index 3ecb71a..56b2569 100644
--- a/include/linux/serial_reg.h
+++ b/include/linux/serial_reg.h
@@ -150,6 +150,7 @@
  * LCR=0xBF (or DLAB=1 for 16C660)
  */
 #define UART_EFR	2	/* I/O: Extended Features Register */
+#define UART_EFR2	9	/* I/O: Extended Features Register for Exari XR17D154 */
 #define UART_EFR_CTS		0x80 /* CTS flow control */
 #define UART_EFR_RTS		0x40 /* RTS flow control */
 #define UART_EFR_SCD		0x20 /* Special character detect */

Re: Hardware flowcontrol on XR17D154

[Alan Cox]

On Tue, 30 Aug 2011 12:17:07 +0200
Søren holm <sgh@sgh.dk> wrote:

> Hi
> 
> I have hacked hardware flowcontrol into 8250.c for the XR17D154. I have 
> attached the patch. The fix just uses another address for the EFR-register.
> 
> I would like to have some adwise as to how to do this the right way. 

Can you explain what the underlying differences are first of all ?

If you just need to adjust a register differently then override
serial_in/serial_out methods and figure out how to detect your device
against others (or a way to probe it somehow).

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Re: Hardware flowcontrol on XR17D154

[Søren holm]

Tirsdag den 30. august 2011 12:34:33 skrev Alan Cox:
> 
> Can you explain what the underlying differences are first of all ?

The EFR register is as you wrote adjusted differently.

> If you just need to adjust a register differently then override
> serial_in/serial_out methods and figure out how to detect your device
> against others (or a way to probe it somehow).

I'm a bit in doubt as to which conclusions I am allowed to draw.

In 'autoconfig_16550a' I can see that a sepcific port type is set;

	if (status1 == 6 && status2 == 7) {
		up->port.type = PORT_16750;
		up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
		return;
	}

My particular uart resports (status1 == 6 && status2 == 6). If that is good 
enough I can add another porttype and add the correct register address as 
UART_EXAR_EFR in the header file.

Another thought could be to write 0xFF (or some other value) to the correct 
EFR-register and read that byte to test if the register is present. The 
problem here is that I do not how the bus reacts to writting/reading invalid 
addresses.

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Re: Hardware flowcontrol on XR17D154

[Alan Cox]

> My particular uart resports (status1 == 6 && status2 == 6). If that is good 
> enough I can add another porttype and add the correct register address as 
> UART_EXAR_EFR in the header file.

Try it and see. We can put it in -next for a while and then there will a
release cycle duriing which any unfortunate clashes wil get resolved.

Alternatively if it's a device attached to a specific platform create it
as a platform device of some kind in the board specific code and pick
that up in the serial driver.

> Another thought could be to write 0xFF (or some other value) to the correct 
> EFR-register and read that byte to test if the register is present. The 
> problem here is that I do not how the bus reacts to writting/reading invalid 
> addresses.

The trouble is an extra register may in fact be part of some other device
- it's generally not a great idea if there are other choices.

Alan

Re: Hardware flowcontrol on XR17D154

[Søren holm]

> > My particular uart resports (status1 == 6 && status2 == 6). If that is
> > good enough I can add another porttype and add the correct register
> > address as UART_EXAR_EFR in the header file.
> 
> Try it and see. We can put it in -next for a while and then there will a
> release cycle duriing which any unfortunate clashes wil get resolved.

I will prepare and test a patch.

> Alternatively if it's a device attached to a specific platform create it
> as a platform device of some kind in the board specific code and pick
> that up in the serial driver.
> 
> > Another thought could be to write 0xFF (or some other value) to the
> > correct EFR-register and read that byte to test if the register is
> > present. The problem here is that I do not how the bus reacts to
> > writting/reading invalid addresses.
> 
> The trouble is an extra register may in fact be part of some other device
> - it's generally not a great idea if there are other choices.

Ok. It did seem like a dangerous thing to do.

Thanks Alan

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Re: Hardware flowcontrol on XR17D154

[Søren holm]

[-- Attachment #1: Type: Text/Plain, Size: 147 bytes --]

Hi

Here is my patch to add EFR-support for XR17D15x
Do you have any comments, since this is my first patch to the kernel ?

-- 
Søren Holm

[-- Attachment #2: 0001-serial-Support-the-EFR-register-of-XR1715x-uarts.patch --]
[-- Type: text/x-patch, Size: 5264 bytes --]

From fcf3746a15af26ddd2e8e2421f81799b15c27707 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?S=C3=B8ren=20Holm?= <sh@mikrofyn.com>
Date: Fri, 2 Sep 2011 12:18:59 +0200
Subject: [PATCH] serial: Support the EFR-register of XR1715x uarts.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The EFR (Enhenced-Features-Register) is located at a different offset
than the other devices supporting UART_CAP_EFR. This change add a special
setup quick to set UPF_EXAR_EFR on the port. UPF_EXAR_EFR is then used to
the port type to PORT_XR17D15X since it is for sure a XR17D15X uart.

Signed-off-by: Søren Holm <sgh@sgh.dk>
---
 drivers/tty/serial/8250.c     |   18 +++++++++++++++++-
 drivers/tty/serial/8250_pci.c |   33 +++++++++++++++++++++++++++++++++
 include/linux/serial_core.h   |    4 +++-
 include/linux/serial_reg.h    |    1 +
 4 files changed, 54 insertions(+), 2 deletions(-)

diff --git a/drivers/tty/serial/8250.c b/drivers/tty/serial/8250.c
index 7f50999..d626ca8 100644
--- a/drivers/tty/serial/8250.c
+++ b/drivers/tty/serial/8250.c
@@ -309,6 +309,13 @@ static const struct serial8250_config uart_config[] = {
 				  UART_FCR_T_TRIG_01,
 		.flags		= UART_CAP_FIFO | UART_CAP_RTOIE,
 	},
+	[PORT_XR17D15X] = {
+		.name		= "XR17D15X",
+		.fifo_size	= 64,
+		.tx_loadsz	= 64,
+		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
+		.flags		= UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR,
+	},
 };
 
 #if defined(CONFIG_MIPS_ALCHEMY)
@@ -1119,6 +1126,12 @@ static void autoconfig_16550a(struct uart_8250_port *up)
 	}
 	serial_outp(up, UART_IER, iersave);
 
+	// Exar uarts have EFR in a weird location
+	if (up->port.flags & UPF_EXAR_EFR) {
+		up->port.type = PORT_XR17D15X;
+		up->capabilities |= UART_CAP_AFE | UART_CAP_EFR;
+	}
+
 	/*
 	 * We distinguish between 16550A and U6 16550A by counting
 	 * how many bytes are in the FIFO.
@@ -2458,7 +2471,10 @@ serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
 			efr |= UART_EFR_CTS;
 
 		serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
-		serial_outp(up, UART_EFR, efr);
+		if (up->port.flags & UPF_EXAR_EFR)
+			serial_outp(up, UART_XR_EFR, efr);
+		else
+			serial_outp(up, UART_EFR, efr);
 	}
 
 #ifdef CONFIG_ARCH_OMAP
diff --git a/drivers/tty/serial/8250_pci.c b/drivers/tty/serial/8250_pci.c
index 3abeca2..52247da 100644
--- a/drivers/tty/serial/8250_pci.c
+++ b/drivers/tty/serial/8250_pci.c
@@ -1101,6 +1101,15 @@ static int pci_eg20t_init(struct pci_dev *dev)
 #endif
 }
 
+static int
+pci_xr17c154_setup(struct serial_private *priv,
+		  const struct pciserial_board *board,
+		  struct uart_port *port, int idx)
+{
+	port->flags |= UPF_EXAR_EFR;
+	return pci_default_setup(priv, board, port, idx);
+}
+
 /* This should be in linux/pci_ids.h */
 #define PCI_VENDOR_ID_SBSMODULARIO	0x124B
 #define PCI_SUBVENDOR_ID_SBSMODULARIO	0x124B
@@ -1506,6 +1515,30 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
 		.setup		= pci_timedia_setup,
 	},
 	/*
+	 * Exar cards
+	 */
+	{
+		.vendor = PCI_VENDOR_ID_EXAR,
+		.device = PCI_DEVICE_ID_EXAR_XR17C152,
+		.subvendor	= PCI_ANY_ID,
+		.subdevice	= PCI_ANY_ID,
+		.setup		= pci_xr17c154_setup,
+	},
+	{
+		.vendor = PCI_VENDOR_ID_EXAR,
+		.device = PCI_DEVICE_ID_EXAR_XR17C154,
+		.subvendor	= PCI_ANY_ID,
+		.subdevice	= PCI_ANY_ID,
+		.setup		= pci_xr17c154_setup,
+	},
+	{
+		.vendor = PCI_VENDOR_ID_EXAR,
+		.device = PCI_DEVICE_ID_EXAR_XR17C158,
+		.subvendor	= PCI_ANY_ID,
+		.subdevice	= PCI_ANY_ID,
+		.setup		= pci_xr17c154_setup,
+	},
+	/*
 	 * Xircom cards
 	 */
 	{
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index a5c3114..01aa96b 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -46,7 +46,8 @@
 #define PORT_AR7	18	/* Texas Instruments AR7 internal UART */
 #define PORT_U6_16550A	19	/* ST-Ericsson U6xxx internal UART */
 #define PORT_TEGRA	20	/* NVIDIA Tegra internal UART */
-#define PORT_MAX_8250	20	/* max port ID */
+#define PORT_XR17D15X	21	/* Exar XR17D15x UART */
+#define PORT_MAX_8250	21	/* max port ID */
 
 /*
  * ARM specific type numbers.  These are not currently guaranteed
@@ -350,6 +351,7 @@ struct uart_port {
 #define UPF_MAGIC_MULTIPLIER	((__force upf_t) (1 << 16))
 #define UPF_CONS_FLOW		((__force upf_t) (1 << 23))
 #define UPF_SHARE_IRQ		((__force upf_t) (1 << 24))
+#define UPF_EXAR_EFR		((__force upf_t) (1 << 25))
 /* The exact UART type is known and should not be probed.  */
 #define UPF_FIXED_TYPE		((__force upf_t) (1 << 27))
 #define UPF_BOOT_AUTOCONF	((__force upf_t) (1 << 28))
diff --git a/include/linux/serial_reg.h b/include/linux/serial_reg.h
index c75bda3..63a749a 100644
--- a/include/linux/serial_reg.h
+++ b/include/linux/serial_reg.h
@@ -152,6 +152,7 @@
  * LCR=0xBF (or DLAB=1 for 16C660)
  */
 #define UART_EFR	2	/* I/O: Extended Features Register */
+#define UART_XR_EFR	9	/* I/O: Extended Features Register for Exar XR17D154 */
 #define UART_EFR_CTS		0x80 /* CTS flow control */
 #define UART_EFR_RTS		0x40 /* RTS flow control */
 #define UART_EFR_SCD		0x20 /* Special character detect */
-- 
1.7.4.1

Re: Hardware flowcontrol on XR17D154

[Alan Cox]

On Fri, 2 Sep 2011 12:20:50 +0200
Søren holm <sgh@sgh.dk> wrote:

> Hi
> 
> Here is my patch to add EFR-support for XR17D15x
> Do you have any comments, since this is my first patch to the kernel ?


Codewise it looks fine

Two things though - run changes through scripts/checkpatch.pl (and it'll
tell you off for the // comment...) and actually inline the patch rather
than attach it so it is easy for people to comment on.

The important bits of it however  - the actual implementation looks right
to me and sensibly implemented.

Possibly it should instead override serial_out/in to use the different EFR
that way but given this is one spot only I don't think its worth the extra
complexity - and if other changes later make it worth doing it's easy to
change.

Alan
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[PATCH] serial: Support the EFR-register of XR1715x uarts.

[Søren Holm]

The EFR (Enhenced-Features-Register) is located at a different offset
than the other devices supporting UART_CAP_EFR. This change add a special
setup quick to set UPF_EXAR_EFR on the port. UPF_EXAR_EFR is then used to
the port type to PORT_XR17D15X since it is for sure a XR17D15X uart.

Signed-off-by: Søren Holm <sgh@sgh.dk>
---
 drivers/tty/serial/8250.c     |   20 +++++++++++++++++++-
 drivers/tty/serial/8250_pci.c |   33 +++++++++++++++++++++++++++++++++
 include/linux/serial_core.h   |    4 +++-
 include/linux/serial_reg.h    |    1 +
 4 files changed, 56 insertions(+), 2 deletions(-)

diff --git a/drivers/tty/serial/8250.c b/drivers/tty/serial/8250.c
index 7f50999..7572666 100644
--- a/drivers/tty/serial/8250.c
+++ b/drivers/tty/serial/8250.c
@@ -309,6 +309,13 @@ static const struct serial8250_config uart_config[] = {
 				  UART_FCR_T_TRIG_01,
 		.flags		= UART_CAP_FIFO | UART_CAP_RTOIE,
 	},
+	[PORT_XR17D15X] = {
+		.name		= "XR17D15X",
+		.fifo_size	= 64,
+		.tx_loadsz	= 64,
+		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
+		.flags		= UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR,
+	},
 };
 
 #if defined(CONFIG_MIPS_ALCHEMY)
@@ -1120,6 +1127,14 @@ static void autoconfig_16550a(struct uart_8250_port *up)
 	serial_outp(up, UART_IER, iersave);
 
 	/*
+	 * Exar uarts have EFR in a weird location
+	 */
+	if (up->port.flags & UPF_EXAR_EFR) {
+		up->port.type = PORT_XR17D15X;
+		up->capabilities |= UART_CAP_AFE | UART_CAP_EFR;
+	}
+
+	/*
 	 * We distinguish between 16550A and U6 16550A by counting
 	 * how many bytes are in the FIFO.
 	 */
@@ -2458,7 +2473,10 @@ serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
 			efr |= UART_EFR_CTS;
 
 		serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
-		serial_outp(up, UART_EFR, efr);
+		if (up->port.flags & UPF_EXAR_EFR)
+			serial_outp(up, UART_XR_EFR, efr);
+		else
+			serial_outp(up, UART_EFR, efr);
 	}
 
 #ifdef CONFIG_ARCH_OMAP
diff --git a/drivers/tty/serial/8250_pci.c b/drivers/tty/serial/8250_pci.c
index 3abeca2..52247da 100644
--- a/drivers/tty/serial/8250_pci.c
+++ b/drivers/tty/serial/8250_pci.c
@@ -1101,6 +1101,15 @@ static int pci_eg20t_init(struct pci_dev *dev)
 #endif
 }
 
+static int
+pci_xr17c154_setup(struct serial_private *priv,
+		  const struct pciserial_board *board,
+		  struct uart_port *port, int idx)
+{
+	port->flags |= UPF_EXAR_EFR;
+	return pci_default_setup(priv, board, port, idx);
+}
+
 /* This should be in linux/pci_ids.h */
 #define PCI_VENDOR_ID_SBSMODULARIO	0x124B
 #define PCI_SUBVENDOR_ID_SBSMODULARIO	0x124B
@@ -1506,6 +1515,30 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
 		.setup		= pci_timedia_setup,
 	},
 	/*
+	 * Exar cards
+	 */
+	{
+		.vendor = PCI_VENDOR_ID_EXAR,
+		.device = PCI_DEVICE_ID_EXAR_XR17C152,
+		.subvendor	= PCI_ANY_ID,
+		.subdevice	= PCI_ANY_ID,
+		.setup		= pci_xr17c154_setup,
+	},
+	{
+		.vendor = PCI_VENDOR_ID_EXAR,
+		.device = PCI_DEVICE_ID_EXAR_XR17C154,
+		.subvendor	= PCI_ANY_ID,
+		.subdevice	= PCI_ANY_ID,
+		.setup		= pci_xr17c154_setup,
+	},
+	{
+		.vendor = PCI_VENDOR_ID_EXAR,
+		.device = PCI_DEVICE_ID_EXAR_XR17C158,
+		.subvendor	= PCI_ANY_ID,
+		.subdevice	= PCI_ANY_ID,
+		.setup		= pci_xr17c154_setup,
+	},
+	/*
 	 * Xircom cards
 	 */
 	{
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index a5c3114..01aa96b 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -46,7 +46,8 @@
 #define PORT_AR7	18	/* Texas Instruments AR7 internal UART */
 #define PORT_U6_16550A	19	/* ST-Ericsson U6xxx internal UART */
 #define PORT_TEGRA	20	/* NVIDIA Tegra internal UART */
-#define PORT_MAX_8250	20	/* max port ID */
+#define PORT_XR17D15X	21	/* Exar XR17D15x UART */
+#define PORT_MAX_8250	21	/* max port ID */
 
 /*
  * ARM specific type numbers.  These are not currently guaranteed
@@ -350,6 +351,7 @@ struct uart_port {
 #define UPF_MAGIC_MULTIPLIER	((__force upf_t) (1 << 16))
 #define UPF_CONS_FLOW		((__force upf_t) (1 << 23))
 #define UPF_SHARE_IRQ		((__force upf_t) (1 << 24))
+#define UPF_EXAR_EFR		((__force upf_t) (1 << 25))
 /* The exact UART type is known and should not be probed.  */
 #define UPF_FIXED_TYPE		((__force upf_t) (1 << 27))
 #define UPF_BOOT_AUTOCONF	((__force upf_t) (1 << 28))
diff --git a/include/linux/serial_reg.h b/include/linux/serial_reg.h
index c75bda3..8ce70d7 100644
--- a/include/linux/serial_reg.h
+++ b/include/linux/serial_reg.h
@@ -152,6 +152,7 @@
  * LCR=0xBF (or DLAB=1 for 16C660)
  */
 #define UART_EFR	2	/* I/O: Extended Features Register */
+#define UART_XR_EFR	9	/* I/O: Extended Features Register (XR17D15x) */
 #define UART_EFR_CTS		0x80 /* CTS flow control */
 #define UART_EFR_RTS		0x40 /* RTS flow control */
 #define UART_EFR_SCD		0x20 /* Special character detect */
-- 
1.7.4.1

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[PATCH] serial: Support the EFR-register of XR1715x uarts.

[Søren Holm]

The EFR (Enhenced-Features-Register) is located at a different offset
than the other devices supporting UART_CAP_EFR. This change add a special
setup quick to set UPF_EXAR_EFR on the port. UPF_EXAR_EFR is then used to
the port type to PORT_XR17D15X since it is for sure a XR17D15X uart.

Signed-off-by: Søren Holm <sgh@sgh.dk>
---
 drivers/tty/serial/8250.c     |   20 +++++++++++++++++++-
 drivers/tty/serial/8250_pci.c |   33 +++++++++++++++++++++++++++++++++
 include/linux/serial_core.h   |    4 +++-
 include/linux/serial_reg.h    |    1 +
 4 files changed, 56 insertions(+), 2 deletions(-)

diff --git a/drivers/tty/serial/8250.c b/drivers/tty/serial/8250.c
index 7f50999..7572666 100644
--- a/drivers/tty/serial/8250.c
+++ b/drivers/tty/serial/8250.c
@@ -309,6 +309,13 @@ static const struct serial8250_config uart_config[] = {
 				  UART_FCR_T_TRIG_01,
 		.flags		= UART_CAP_FIFO | UART_CAP_RTOIE,
 	},
+	[PORT_XR17D15X] = {
+		.name		= "XR17D15X",
+		.fifo_size	= 64,
+		.tx_loadsz	= 64,
+		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
+		.flags		= UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR,
+	},
 };
 
 #if defined(CONFIG_MIPS_ALCHEMY)
@@ -1120,6 +1127,14 @@ static void autoconfig_16550a(struct uart_8250_port *up)
 	serial_outp(up, UART_IER, iersave);
 
 	/*
+	 * Exar uarts have EFR in a weird location
+	 */
+	if (up->port.flags & UPF_EXAR_EFR) {
+		up->port.type = PORT_XR17D15X;
+		up->capabilities |= UART_CAP_AFE | UART_CAP_EFR;
+	}
+
+	/*
 	 * We distinguish between 16550A and U6 16550A by counting
 	 * how many bytes are in the FIFO.
 	 */
@@ -2458,7 +2473,10 @@ serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
 			efr |= UART_EFR_CTS;
 
 		serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
-		serial_outp(up, UART_EFR, efr);
+		if (up->port.flags & UPF_EXAR_EFR)
+			serial_outp(up, UART_XR_EFR, efr);
+		else
+			serial_outp(up, UART_EFR, efr);
 	}
 
 #ifdef CONFIG_ARCH_OMAP
diff --git a/drivers/tty/serial/8250_pci.c b/drivers/tty/serial/8250_pci.c
index 3abeca2..52247da 100644
--- a/drivers/tty/serial/8250_pci.c
+++ b/drivers/tty/serial/8250_pci.c
@@ -1101,6 +1101,15 @@ static int pci_eg20t_init(struct pci_dev *dev)
 #endif
 }
 
+static int
+pci_xr17c154_setup(struct serial_private *priv,
+		  const struct pciserial_board *board,
+		  struct uart_port *port, int idx)
+{
+	port->flags |= UPF_EXAR_EFR;
+	return pci_default_setup(priv, board, port, idx);
+}
+
 /* This should be in linux/pci_ids.h */
 #define PCI_VENDOR_ID_SBSMODULARIO	0x124B
 #define PCI_SUBVENDOR_ID_SBSMODULARIO	0x124B
@@ -1506,6 +1515,30 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
 		.setup		= pci_timedia_setup,
 	},
 	/*
+	 * Exar cards
+	 */
+	{
+		.vendor = PCI_VENDOR_ID_EXAR,
+		.device = PCI_DEVICE_ID_EXAR_XR17C152,
+		.subvendor	= PCI_ANY_ID,
+		.subdevice	= PCI_ANY_ID,
+		.setup		= pci_xr17c154_setup,
+	},
+	{
+		.vendor = PCI_VENDOR_ID_EXAR,
+		.device = PCI_DEVICE_ID_EXAR_XR17C154,
+		.subvendor	= PCI_ANY_ID,
+		.subdevice	= PCI_ANY_ID,
+		.setup		= pci_xr17c154_setup,
+	},
+	{
+		.vendor = PCI_VENDOR_ID_EXAR,
+		.device = PCI_DEVICE_ID_EXAR_XR17C158,
+		.subvendor	= PCI_ANY_ID,
+		.subdevice	= PCI_ANY_ID,
+		.setup		= pci_xr17c154_setup,
+	},
+	/*
 	 * Xircom cards
 	 */
 	{
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index a5c3114..01aa96b 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -46,7 +46,8 @@
 #define PORT_AR7	18	/* Texas Instruments AR7 internal UART */
 #define PORT_U6_16550A	19	/* ST-Ericsson U6xxx internal UART */
 #define PORT_TEGRA	20	/* NVIDIA Tegra internal UART */
-#define PORT_MAX_8250	20	/* max port ID */
+#define PORT_XR17D15X	21	/* Exar XR17D15x UART */
+#define PORT_MAX_8250	21	/* max port ID */
 
 /*
  * ARM specific type numbers.  These are not currently guaranteed
@@ -350,6 +351,7 @@ struct uart_port {
 #define UPF_MAGIC_MULTIPLIER	((__force upf_t) (1 << 16))
 #define UPF_CONS_FLOW		((__force upf_t) (1 << 23))
 #define UPF_SHARE_IRQ		((__force upf_t) (1 << 24))
+#define UPF_EXAR_EFR		((__force upf_t) (1 << 25))
 /* The exact UART type is known and should not be probed.  */
 #define UPF_FIXED_TYPE		((__force upf_t) (1 << 27))
 #define UPF_BOOT_AUTOCONF	((__force upf_t) (1 << 28))
diff --git a/include/linux/serial_reg.h b/include/linux/serial_reg.h
index c75bda3..8ce70d7 100644
--- a/include/linux/serial_reg.h
+++ b/include/linux/serial_reg.h
@@ -152,6 +152,7 @@
  * LCR=0xBF (or DLAB=1 for 16C660)
  */
 #define UART_EFR	2	/* I/O: Extended Features Register */
+#define UART_XR_EFR	9	/* I/O: Extended Features Register (XR17D15x) */
 #define UART_EFR_CTS		0x80 /* CTS flow control */
 #define UART_EFR_RTS		0x40 /* RTS flow control */
 #define UART_EFR_SCD		0x20 /* Special character detect */
-- 
1.7.4.1

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Re: Hardware flowcontrol on XR17D154

[Søren holm]

I cleaned up the style issues in my previous mails.

Sorry for the double posting. The maillist was problably slower that my 
partience could bear :)

-- 
Søren Holm
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Re: [PATCH] serial: Support the EFR-register of XR1715x uarts.

[Alan Cox]

On Fri,  2 Sep 2011 22:55:37 +0200
Søren Holm <sgh@sgh.dk> wrote:

> The EFR (Enhenced-Features-Register) is located at a different offset
> than the other devices supporting UART_CAP_EFR. This change add a special
> setup quick to set UPF_EXAR_EFR on the port. UPF_EXAR_EFR is then used to
> the port type to PORT_XR17D15X since it is for sure a XR17D15X uart.
> 
> Signed-off-by: Søren Holm <sgh@sgh.dk>

Acked-by: Alan Cox <alan@linux.intel.com>
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