From: Theodore Ts'o <tytso@mit.edu>
To: Prasad Koya <prasad.koya@gmail.com>
Cc: linux-serial@vger.kernel.org, gregkh@linuxfoundation.org
Subject: Re: UART_IIR_BUSY set for 16550A
Date: Thu, 29 May 2014 02:18:37 -0400 [thread overview]
Message-ID: <20140529061837.GD25041@thunk.org> (raw)
In-Reply-To: <CAGXD9OdyXxpVZVR44N-ZKe5Nwz9EVbH_YgZncVbskRfsAq6Htw@mail.gmail.com>
On Tue, May 27, 2014 at 10:47:05PM -0700, Prasad Koya wrote:
>
> if char received is garbage then as you hinted it must be that
> transmit ready interrupt that is not getting set.
This was typo on my part. What I meant to say was that it is the
"receive ready interrupt" (not transmit) getting set when it shouldn't
be.
That is, the fact that DR bit was clear was indeed correct --- the
receive FIFO really was empty, but for some reason some other part of
the UART was convinced that it should be trying to trigger a receive
interrupt, hence the value in IIR.
In that case, if you force the DR bit to be set, then you'll be
looping forever loading garbage into the tty flip buffer until it
overflows. This is why I said you should put in a counter that only
does this workaround a limited number of times, and which point you
send a printk of the saying "Buggy Intel UART, abandon all hope", and
then submit a patch to the kernel cc'ing someone from Intel, in the
hopes that they will fix the bug....
Cheers,
- Ted
prev parent reply other threads:[~2014-05-29 6:18 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-23 17:08 UART_IIR_BUSY set for 16550A Prasad Koya
2014-05-25 0:36 ` Theodore Ts'o
2014-05-25 1:22 ` Prasad Koya
2014-05-25 2:44 ` Theodore Ts'o
2014-05-25 6:21 ` Prasad Koya
2014-05-25 12:04 ` Theodore Ts'o
2014-05-27 23:33 ` Prasad Koya
2014-05-28 5:03 ` Theodore Ts'o
2014-05-28 5:47 ` Prasad Koya
2014-05-29 6:18 ` Theodore Ts'o [this message]
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