[PATCH 0/7] ARM: meson: add preliminary support for MesonX/Meson6 SoCs

[PATCH 0/7] ARM: meson: add preliminary support for MesonX/Meson6 SoCs

[Carlo Caione]

Amlogic AML8726-MX (codename Meson6) is a highly integrated multimedia
application processor SoC for Multimedia Internet Device (MID), tablet
and Set Top Box (STB). It integrates a powerful CPU, a 2D/3D graphics
subsystem and a state-of-the-art video decoding engine together with
all major peripherals. It is manufactured by Amlogic, inc.

This patchset introduces preliminary support for Meson6-based SoCs but
several IPs and drivers are common among all the MesonX SoCs.

Amlogic doesn't release any documentation about their SoCs, so the code
has been reverse-engineered from the messy source code released at:

http://openlinux.amlogic.com:8000/download/

Carlo Caione (7):
  ARM: meson: debug: add debug UART for earlyprintk support
  ARM: meson: serial: add MesonX SoC on-chip uart driver
  ARM: meson6: clocksource: add Meson6 timer support
  ARM: meson: add basic support for MesonX SoCs
  ARM: meson: dts: add basic Meson/Meson6/Meson6-atv1200 DTSI/DTS
  ARM: meson: update defconfigs
  ARM: meson: update documentation (uart, timer and vendors)

 .../bindings/serial/amlogic,meson-uart.txt         |  17 +
 .../bindings/timer/amlogic,meson6-timer.txt        |  16 +
 .../devicetree/bindings/vendor-prefixes.txt        |   1 +
 arch/arm/Kconfig                                   |   2 +
 arch/arm/Kconfig.debug                             |  14 +-
 arch/arm/Makefile                                  |   1 +
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/meson.dtsi                       |  75 +++
 arch/arm/boot/dts/meson6-atv1200.dts               |  27 +
 arch/arm/boot/dts/meson6.dtsi                      |  44 ++
 arch/arm/configs/meson_defconfig                   |  99 ++++
 arch/arm/configs/multi_v7_defconfig                |   3 +
 arch/arm/include/debug/meson.S                     |  35 ++
 arch/arm/mach-meson/Kconfig                        |  13 +
 arch/arm/mach-meson/Makefile                       |   1 +
 arch/arm/mach-meson/meson.c                        |  36 ++
 drivers/clocksource/Kconfig                        |   3 +
 drivers/clocksource/Makefile                       |   1 +
 drivers/clocksource/meson6_timer.c                 | 187 ++++++
 drivers/tty/serial/Kconfig                         |  18 +
 drivers/tty/serial/Makefile                        |   1 +
 drivers/tty/serial/meson_uart.c                    | 634 +++++++++++++++++++++
 include/uapi/linux/serial_core.h                   |   3 +
 23 files changed, 1230 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt
 create mode 100644 Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt
 create mode 100644 arch/arm/boot/dts/meson.dtsi
 create mode 100644 arch/arm/boot/dts/meson6-atv1200.dts
 create mode 100644 arch/arm/boot/dts/meson6.dtsi
 create mode 100644 arch/arm/configs/meson_defconfig
 create mode 100644 arch/arm/include/debug/meson.S
 create mode 100644 arch/arm/mach-meson/Kconfig
 create mode 100644 arch/arm/mach-meson/Makefile
 create mode 100644 arch/arm/mach-meson/meson.c
 create mode 100644 drivers/clocksource/meson6_timer.c
 create mode 100644 drivers/tty/serial/meson_uart.c

-- 
1.9.1

[PATCH 1/7] ARM: meson: debug: add debug UART for earlyprintk support

[Carlo Caione]

Add the UART definitions needed to support earlyprintk for MesonX SoCs
on UARTAO.

Signed-off-by: Carlo Caione <carlo@caione.org>
---
 arch/arm/Kconfig.debug         | 14 ++++++++++++--
 arch/arm/include/debug/meson.S | 35 +++++++++++++++++++++++++++++++++++
 2 files changed, 47 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/include/debug/meson.S

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index b11ad54..16079c5 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -348,6 +348,13 @@ choice
 		  Say Y here if you want the debug print routines to direct
 		  their output to UART1 serial port on KEYSTONE2 devices.
 
+	config DEBUG_MESON_UARTAO
+		bool "Kernel low-level debugging via Meson6 UARTAO"
+		depends on ARCH_MESON
+		help
+		  Say Y here if you want kernel low-lever debugging support
+		  on Amlogic Meson6 based platforms on the UARTAO.
+
 	config DEBUG_MMP_UART2
 		bool "Kernel low-level debugging message via MMP UART2"
 		depends on ARCH_MMP
@@ -1011,6 +1018,7 @@ config DEBUG_LL_INCLUDE
 	string
 	default "debug/8250.S" if DEBUG_LL_UART_8250 || DEBUG_UART_8250
 	default "debug/clps711x.S" if DEBUG_CLPS711X_UART1 || DEBUG_CLPS711X_UART2
+	default "debug/meson.S" if DEBUG_MESON_UARTAO
 	default "debug/pl01x.S" if DEBUG_LL_UART_PL01X || DEBUG_UART_PL01X
 	default "debug/exynos.S" if DEBUG_EXYNOS_UART
 	default "debug/efm32.S" if DEBUG_LL_UART_EFM32
@@ -1106,6 +1114,7 @@ config DEBUG_UART_PHYS
 	default 0xc8000003 if ARCH_IXP4XX && CPU_BIG_ENDIAN
 	default 0xd0000000 if ARCH_SPEAR3XX || ARCH_SPEAR6XX
 	default 0xd0012000 if DEBUG_MVEBU_UART
+	default 0xc81004c0 if DEBUG_MESON_UARTAO
 	default 0xd4017000 if DEBUG_MMP_UART2
 	default 0xd4018000 if DEBUG_MMP_UART3
 	default 0xe0000000 if ARCH_SPEAR13XX
@@ -1125,7 +1134,7 @@ config DEBUG_UART_PHYS
 	default 0xfffff700 if ARCH_IOP33X
 	depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
 		DEBUG_LL_UART_EFM32 || \
-		DEBUG_UART_8250 || DEBUG_UART_PL01X || \
+		DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \
 		DEBUG_MSM_UART || DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART
 
 config DEBUG_UART_VIRT
@@ -1162,6 +1171,7 @@ config DEBUG_UART_VIRT
 	default 0xfd012000 if ARCH_MV78XX0
 	default 0xfde12000 if ARCH_DOVE
 	default 0xfe012000 if ARCH_ORION5X
+	default 0xf31004c0 if DEBUG_MESON_UARTAO
 	default 0xfe017000 if DEBUG_MMP_UART2
 	default 0xfe018000 if DEBUG_MMP_UART3
 	default 0xfe100000 if DEBUG_IMX23_UART || DEBUG_IMX28_UART
@@ -1193,7 +1203,7 @@ config DEBUG_UART_VIRT
 	default 0xff003000 if DEBUG_U300_UART
 	default DEBUG_UART_PHYS if !MMU
 	depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
-		DEBUG_UART_8250 || DEBUG_UART_PL01X || \
+		DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \
 		DEBUG_MSM_UART || DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART
 
 config DEBUG_UART_8250_SHIFT
diff --git a/arch/arm/include/debug/meson.S b/arch/arm/include/debug/meson.S
new file mode 100644
index 0000000..1bae99b
--- /dev/null
+++ b/arch/arm/include/debug/meson.S
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2014 Carlo Caione
+ * Carlo Caione <carlo@caione.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define MESON_AO_UART_WFIFO		0x0
+#define MESON_AO_UART_STATUS		0xc
+
+#define MESON_AO_UART_TX_FIFO_EMPTY	(1 << 22)
+#define MESON_AO_UART_TX_FIFO_FULL	(1 << 21)
+
+	.macro	addruart, rp, rv, tmp
+	ldr	\rp, =(CONFIG_DEBUG_UART_PHYS)		@ physical
+	ldr	\rv, =(CONFIG_DEBUG_UART_VIRT)		@ virtual
+	.endm
+
+	.macro	senduart,rd,rx
+	str	\rd, [\rx, #MESON_AO_UART_WFIFO]
+	.endm
+
+	.macro	busyuart,rd,rx
+1002:	ldr	\rd, [\rx, #MESON_AO_UART_STATUS]
+	tst	\rd, #MESON_AO_UART_TX_FIFO_EMPTY
+	beq	1002b
+	.endm
+
+	.macro	waituart,rd,rx
+1001:	ldr	\rd, [\rx, #MESON_AO_UART_STATUS]
+	tst	\rd, #MESON_AO_UART_TX_FIFO_FULL
+	bne	1001b
+	.endm
-- 
1.9.1

[PATCH 2/7] ARM: meson: serial: add MesonX SoC on-chip uart driver

[Carlo Caione]

The SoC has four fully functional UARTs which use the same programming
model. They are named UART_A, UART_B, UART_C and UART_AO (Always-On)
which cannot be powered off.

Signed-off-by: Carlo Caione <carlo@caione.org>
---
 drivers/tty/serial/Kconfig       |  18 ++
 drivers/tty/serial/Makefile      |   1 +
 drivers/tty/serial/meson_uart.c  | 634 +++++++++++++++++++++++++++++++++++++++
 include/uapi/linux/serial_core.h |   3 +
 4 files changed, 656 insertions(+)
 create mode 100644 drivers/tty/serial/meson_uart.c

diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 26cec64..929b85e 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -200,6 +200,24 @@ config SERIAL_KS8695_CONSOLE
 	  receives all kernel messages and warnings and which allows
 	  logins in single user mode).
 
+config SERIAL_MESON
+	tristate "Meson serial port support"
+	depends on ARCH_MESON
+	select SERIAL_CORE
+	help
+	  This enables the driver for the on-chip UARTs of the Amlogic
+	  MesonX processors.
+
+config SERIAL_MESON_CONSOLE
+	bool "Support for console on meson"
+	depends on SERIAL_MESON=y
+	select SERIAL_CORE_CONSOLE
+	help
+	  Say Y here if you wish to use a Amlogic MesonX UART as the
+	  system console (the system console is the device which
+	  receives all kernel messages and warnings and which allows
+	  logins in single user mode) as /dev/ttyAMLx.
+
 config SERIAL_CLPS711X
 	tristate "CLPS711X serial port support"
 	depends on ARCH_CLPS711X || COMPILE_TEST
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index 0080cc3..9a548ac 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -48,6 +48,7 @@ obj-$(CONFIG_SERIAL_MPC52xx) += mpc52xx_uart.o
 obj-$(CONFIG_SERIAL_ICOM) += icom.o
 obj-$(CONFIG_SERIAL_M32R_SIO) += m32r_sio.o
 obj-$(CONFIG_SERIAL_MPSC) += mpsc.o
+obj-$(CONFIG_SERIAL_MESON) += meson_uart.o
 obj-$(CONFIG_SERIAL_SB1250_DUART) += sb1250-duart.o
 obj-$(CONFIG_ETRAX_SERIAL) += crisv10.o
 obj-$(CONFIG_SERIAL_SCCNXP) += sccnxp.o
diff --git a/drivers/tty/serial/meson_uart.c b/drivers/tty/serial/meson_uart.c
new file mode 100644
index 0000000..15c7497
--- /dev/null
+++ b/drivers/tty/serial/meson_uart.c
@@ -0,0 +1,634 @@
+/*
+ *  Based on meson_uart.c, by AMLOGIC, INC.
+ *
+ * Copyright (C) 2014 Carlo Caione <carlo@caione.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+
+/* Register offsets */
+#define AML_UART_WFIFO			0x00
+#define AML_UART_RFIFO			0x04
+#define AML_UART_CONTROL		0x08
+#define AML_UART_STATUS			0x0c
+#define AML_UART_MISC			0x10
+#define AML_UART_REG5			0x14
+
+/* AML_UART_CONTROL bits */
+#define AML_UART_TX_EN			BIT(12)
+#define AML_UART_RX_EN			BIT(13)
+#define AML_UART_TX_RST			BIT(22)
+#define AML_UART_RX_RST			BIT(23)
+#define AML_UART_CLR_ERR		BIT(24)
+#define AML_UART_RX_INT_EN		BIT(27)
+#define AML_UART_TX_INT_EN		BIT(28)
+#define AML_UART_DATA_LEN_MASK		(0x03 << 20)
+#define AML_UART_DATA_LEN_8BIT		(0x00 << 20)
+#define AML_UART_DATA_LEN_7BIT		(0x01 << 20)
+#define AML_UART_DATA_LEN_6BIT		(0x02 << 20)
+#define AML_UART_DATA_LEN_5BIT		(0x03 << 20)
+
+/* AML_UART_STATUS bits */
+#define AML_UART_PARITY_ERR		BIT(16)
+#define AML_UART_FRAME_ERR		BIT(17)
+#define AML_UART_TX_FIFO_WERR		BIT(18)
+#define AML_UART_RX_EMPTY		BIT(20)
+#define AML_UART_TX_FULL		BIT(21)
+#define AML_UART_TX_EMPTY		BIT(22)
+#define AML_UART_ERR			(AML_UART_PARITY_ERR | \
+					 AML_UART_FRAME_ERR  | \
+					 AML_UART_TX_FIFO_WERR)
+
+/* AML_UART_CONTROL bits */
+#define AML_UART_TWO_WIRE_EN		BIT(15)
+#define AML_UART_PARITY_TYPE		BIT(18)
+#define AML_UART_PARITY_EN		BIT(19)
+#define AML_UART_CLEAR_ERR		BIT(24)
+#define AML_UART_STOP_BIN_LEN_MASK	(0x03 << 16)
+#define AML_UART_STOP_BIN_1SB		(0x00 << 16)
+#define AML_UART_STOP_BIN_2SB		(0x01 << 16)
+
+/* AML_UART_MISC bits */
+#define AML_UART_XMIT_IRQ(c)		(((c) & 0xff) << 8)
+#define AML_UART_RECV_IRQ(c)		((c) & 0xff)
+
+/* AML_UART_REG5 bits */
+#define AML_UART_BAUD_MASK		0x7fffff
+#define AML_UART_BAUD_USE		BIT(23)
+
+#define AML_UART_PORT_NUM		6
+#define AML_UART_DEV_NAME		"ttyAML"
+
+
+static struct uart_driver meson_uart_driver;
+
+static struct uart_port *meson_ports[AML_UART_PORT_NUM];
+
+static void meson_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+}
+
+static unsigned int meson_uart_get_mctrl(struct uart_port *port)
+{
+	return TIOCM_CTS;
+}
+
+static unsigned int meson_uart_tx_empty(struct uart_port *port)
+{
+	u32 val;
+
+	val = readl(port->membase + AML_UART_STATUS);
+	return (val & AML_UART_TX_EMPTY) ? TIOCSER_TEMT : 0;
+}
+
+static void meson_uart_stop_tx(struct uart_port *port)
+{
+	u32 val;
+
+	val = readl(port->membase + AML_UART_CONTROL);
+	val &= ~AML_UART_TX_EN;
+	writel(val, port->membase + AML_UART_CONTROL);
+}
+
+static void meson_uart_stop_rx(struct uart_port *port)
+{
+	u32 val;
+
+	val = readl(port->membase + AML_UART_CONTROL);
+	val &= ~AML_UART_RX_EN;
+	writel(val, port->membase + AML_UART_CONTROL);
+}
+
+static void meson_uart_shutdown(struct uart_port *port)
+{
+	unsigned long flags;
+	u32 val;
+
+	free_irq(port->irq, port);
+
+	spin_lock_irqsave(&port->lock, flags);
+
+	val = readl(port->membase + AML_UART_CONTROL);
+	val &= ~(AML_UART_RX_EN | AML_UART_TX_EN);
+	val &= ~(AML_UART_RX_INT_EN | AML_UART_TX_INT_EN);
+	writel(val, port->membase + AML_UART_CONTROL);
+
+	spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static void meson_uart_start_tx(struct uart_port *port)
+{
+	struct circ_buf *xmit = &port->state->xmit;
+	unsigned int ch;
+
+	if (uart_tx_stopped(port)) {
+		meson_uart_stop_tx(port);
+		return;
+	}
+
+	while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) {
+		if (port->x_char) {
+			writel(port->x_char, port->membase + AML_UART_WFIFO);
+			port->icount.tx++;
+			port->x_char = 0;
+			continue;
+		}
+
+		if (uart_circ_empty(xmit))
+			break;
+
+		ch = xmit->buf[xmit->tail];
+		writel(ch, port->membase + AML_UART_WFIFO);
+		xmit->tail = (xmit->tail+1) & (SERIAL_XMIT_SIZE - 1);
+		port->icount.tx++;
+	}
+
+	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+		uart_write_wakeup(port);
+}
+
+static void meson_receive_chars(struct uart_port *port)
+{
+	struct tty_port *tport = &port->state->port;
+	char flag;
+	u32 status, ch, mode;
+
+	do {
+		flag = TTY_NORMAL;
+		port->icount.rx++;
+		status = readl(port->membase + AML_UART_STATUS);
+
+		if (status & AML_UART_ERR) {
+			if (status & AML_UART_TX_FIFO_WERR)
+				port->icount.overrun++;
+			else if (status & AML_UART_FRAME_ERR)
+				port->icount.frame++;
+			else if (status & AML_UART_PARITY_ERR)
+				port->icount.frame++;
+
+			mode = readl(port->membase + AML_UART_CONTROL);
+			mode |= AML_UART_CLEAR_ERR;
+			writel(mode, port->membase + AML_UART_CONTROL);
+
+			/* It doesn't clear to 0 automatically */
+			mode &= ~AML_UART_CLEAR_ERR;
+			writel(mode, port->membase + AML_UART_CONTROL);
+
+			status &= port->read_status_mask;
+			if (status & AML_UART_FRAME_ERR)
+				flag = TTY_FRAME;
+			else if (status & AML_UART_PARITY_ERR)
+				flag = TTY_PARITY;
+		}
+
+		ch = readl(port->membase + AML_UART_RFIFO);
+		ch &= 0xff;
+
+		if ((status & port->ignore_status_mask) == 0)
+			tty_insert_flip_char(tport, ch, flag);
+
+		if (status & AML_UART_TX_FIFO_WERR)
+			tty_insert_flip_char(tport, 0, TTY_OVERRUN);
+
+	} while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY));
+
+	spin_unlock(&port->lock);
+	tty_flip_buffer_push(tport);
+	spin_lock(&port->lock);
+}
+
+static irqreturn_t meson_uart_interrupt(int irq, void *dev_id)
+{
+	struct uart_port *port = (struct uart_port *)dev_id;
+
+	spin_lock(&port->lock);
+
+	if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY))
+		meson_receive_chars(port);
+
+	if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL))
+		meson_uart_start_tx(port);
+
+	spin_unlock(&port->lock);
+
+	return IRQ_HANDLED;
+}
+
+static const char *meson_uart_type(struct uart_port *port)
+{
+	return (port->type == PORT_MESON) ? "meson_uart" : NULL;
+}
+
+static int meson_uart_startup(struct uart_port *port)
+{
+	u32 val;
+	int ret = 0;
+
+	val = readl(port->membase + AML_UART_CONTROL);
+	val |= (AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLR_ERR);
+	writel(val, port->membase + AML_UART_CONTROL);
+
+	val &= ~(AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLR_ERR);
+	writel(val, port->membase + AML_UART_CONTROL);
+
+	val |= (AML_UART_RX_EN | AML_UART_TX_EN);
+	writel(val, port->membase + AML_UART_CONTROL);
+
+	val |= (AML_UART_RX_INT_EN | AML_UART_TX_INT_EN);
+	writel(val, port->membase + AML_UART_CONTROL);
+
+	val = (AML_UART_RECV_IRQ(1) | AML_UART_XMIT_IRQ(port->fifosize / 2));
+	writel(val, port->membase + AML_UART_MISC);
+
+	ret = request_irq(port->irq, meson_uart_interrupt, 0,
+			  meson_uart_type(port), port);
+
+	return ret;
+}
+
+static void meson_uart_change_speed(struct uart_port *port, unsigned long baud)
+{
+	u32 val;
+
+	while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_EMPTY))
+		cpu_relax();
+
+	val = readl(port->membase + AML_UART_REG5);
+	val &= ~AML_UART_BAUD_MASK;
+	val = ((port->uartclk * 10 / (baud * 4) + 5) / 10) - 1;
+	val |= AML_UART_BAUD_USE;
+	writel(val, port->membase + AML_UART_REG5);
+}
+
+static void meson_uart_set_termios(struct uart_port *port,
+				   struct ktermios *termios,
+				   struct ktermios *old)
+{
+	unsigned int cflags, iflags, baud;
+	unsigned long flags;
+	u32 val;
+
+	spin_lock_irqsave(&port->lock, flags);
+
+	cflags = termios->c_cflag;
+	iflags = termios->c_iflag;
+
+	val = readl(port->membase + AML_UART_CONTROL);
+
+	val &= ~AML_UART_DATA_LEN_MASK;
+	switch (cflags & CSIZE) {
+	case CS8:
+		val |= AML_UART_DATA_LEN_8BIT;
+		break;
+	case CS7:
+		val |= AML_UART_DATA_LEN_7BIT;
+		break;
+	case CS6:
+		val |= AML_UART_DATA_LEN_6BIT;
+		break;
+	case CS5:
+		val |= AML_UART_DATA_LEN_5BIT;
+		break;
+	}
+
+	if (cflags & PARENB)
+		val |= AML_UART_PARITY_EN;
+	else
+		val &= ~AML_UART_PARITY_EN;
+
+	if (cflags & PARODD)
+		val |= AML_UART_PARITY_TYPE;
+	else
+		val &= ~AML_UART_PARITY_TYPE;
+
+	val &= ~AML_UART_STOP_BIN_LEN_MASK;
+	if (cflags & CSTOPB)
+		val |= AML_UART_STOP_BIN_2SB;
+	else
+		val &= ~AML_UART_STOP_BIN_1SB;
+
+	if (cflags & CRTSCTS)
+		val &= ~AML_UART_TWO_WIRE_EN;
+	else
+		val |= AML_UART_TWO_WIRE_EN;
+
+	writel(val, port->membase + AML_UART_CONTROL);
+
+	baud = uart_get_baud_rate(port, termios, old, 9600, 115200);
+	meson_uart_change_speed(port, baud);
+
+	port->read_status_mask = AML_UART_TX_FIFO_WERR;
+	if (iflags & INPCK)
+		port->read_status_mask |= AML_UART_PARITY_ERR |
+					  AML_UART_FRAME_ERR;
+
+	port->ignore_status_mask = 0;
+	if (iflags & IGNPAR)
+		port->ignore_status_mask |= AML_UART_PARITY_ERR |
+					    AML_UART_FRAME_ERR;
+
+	uart_update_timeout(port, termios->c_cflag, baud);
+	spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static int meson_uart_verify_port(struct uart_port *port,
+				  struct serial_struct *ser)
+{
+	int ret = 0;
+
+	if (port->type != PORT_MESON)
+		ret = -EINVAL;
+	if (port->irq != ser->irq)
+		ret = -EINVAL;
+	if (ser->baud_base < 9600)
+		ret = -EINVAL;
+	return ret;
+}
+
+static void meson_uart_release_port(struct uart_port *port)
+{
+	if (port->flags & UPF_IOREMAP) {
+		iounmap(port->membase);
+		port->membase = NULL;
+	}
+}
+
+static int meson_uart_request_port(struct uart_port *port)
+{
+	struct platform_device *pdev = to_platform_device(port->dev);
+	struct resource *res;
+	int size;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "cannot obtain I/O memory region");
+		return -ENODEV;
+	}
+	size = resource_size(res);
+
+	if (!devm_request_mem_region(port->dev, port->mapbase, size,
+				     dev_name(port->dev))) {
+		dev_err(port->dev, "Memory region busy\n");
+		return -EBUSY;
+	}
+
+	if (port->flags & UPF_IOREMAP) {
+		port->membase = devm_ioremap_nocache(port->dev,
+						     port->mapbase,
+						     size);
+		if (port->membase == NULL)
+			return -ENOMEM;
+	}
+
+	return 0;
+}
+
+static void meson_uart_config_port(struct uart_port *port, int flags)
+{
+	if (flags & UART_CONFIG_TYPE) {
+		port->type = PORT_MESON;
+		meson_uart_request_port(port);
+	}
+}
+
+static struct uart_ops meson_uart_ops = {
+	.set_mctrl      = meson_uart_set_mctrl,
+	.get_mctrl      = meson_uart_get_mctrl,
+	.tx_empty	= meson_uart_tx_empty,
+	.start_tx	= meson_uart_start_tx,
+	.stop_tx	= meson_uart_stop_tx,
+	.stop_rx	= meson_uart_stop_rx,
+	.startup	= meson_uart_startup,
+	.shutdown	= meson_uart_shutdown,
+	.set_termios	= meson_uart_set_termios,
+	.type		= meson_uart_type,
+	.config_port	= meson_uart_config_port,
+	.request_port	= meson_uart_request_port,
+	.release_port	= meson_uart_release_port,
+	.verify_port	= meson_uart_verify_port,
+};
+
+#ifdef CONFIG_SERIAL_MESON_CONSOLE
+
+static void meson_console_putchar(struct uart_port *port, int ch)
+{
+	if (!port->membase)
+		return;
+
+	while (readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)
+		cpu_relax();
+	writel(ch, port->membase + AML_UART_WFIFO);
+}
+
+static void meson_serial_console_write(struct console *co, const char *s,
+				       u_int count)
+{
+	struct uart_port *port;
+	unsigned long flags;
+	int locked;
+
+	port = meson_ports[co->index];
+	if (!port)
+		return;
+
+	local_irq_save(flags);
+	if (port->sysrq) {
+		locked = 0;
+	} else if (oops_in_progress) {
+		locked = spin_trylock(&port->lock);
+	} else {
+		spin_lock(&port->lock);
+		locked = 1;
+	}
+
+	uart_console_write(port, s, count, meson_console_putchar);
+
+	if (locked)
+		spin_unlock(&port->lock);
+	local_irq_restore(flags);
+}
+
+static int meson_serial_console_setup(struct console *co, char *options)
+{
+	struct uart_port *port;
+	int baud = 115200;
+	int bits = 8;
+	int parity = 'n';
+	int flow = 'n';
+
+	if (co->index < 0 || co->index >= AML_UART_PORT_NUM)
+		return -EINVAL;
+
+	port = meson_ports[co->index];
+	if (!port || !port->membase)
+		return -ENODEV;
+
+	if (options)
+		uart_parse_options(options, &baud, &parity, &bits, &flow);
+
+	return uart_set_options(port, co, baud, parity, bits, flow);
+}
+
+static struct console meson_serial_console = {
+	.name		= AML_UART_DEV_NAME,
+	.write		= meson_serial_console_write,
+	.device		= uart_console_device,
+	.setup		= meson_serial_console_setup,
+	.flags		= CON_PRINTBUFFER,
+	.index		= -1,
+	.data		= &meson_uart_driver,
+};
+
+static int __init meson_serial_console_init(void)
+{
+	register_console(&meson_serial_console);
+	return 0;
+}
+console_initcall(meson_serial_console_init);
+
+#define MESON_SERIAL_CONSOLE	(&meson_serial_console)
+#else
+#define MESON_SERIAL_CONSOLE	NULL
+#endif
+
+static struct uart_driver meson_uart_driver = {
+	.owner		= THIS_MODULE,
+	.driver_name	= "meson_uart",
+	.dev_name	= AML_UART_DEV_NAME,
+	.nr		= AML_UART_PORT_NUM,
+	.cons		= MESON_SERIAL_CONSOLE,
+};
+
+static int meson_uart_probe(struct platform_device *pdev)
+{
+	struct resource *res_mem, *res_irq;
+	struct uart_port *port;
+	struct clk *clk;
+	int ret = 0;
+
+	if (pdev->dev.of_node)
+		pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
+
+	if (pdev->id < 0 || pdev->id >= AML_UART_PORT_NUM)
+		return -EINVAL;
+
+	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res_mem)
+		return -ENODEV;
+
+	res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (!res_irq)
+		return -ENODEV;
+
+	if (meson_ports[pdev->id]) {
+		dev_err(&pdev->dev, "port %d already allocated\n", pdev->id);
+		return -EBUSY;
+	}
+
+	port = devm_kzalloc(&pdev->dev, sizeof(struct uart_port), GFP_KERNEL);
+	if (!port)
+		return -ENOMEM;
+
+	clk = clk_get(&pdev->dev, NULL);
+	if (IS_ERR(clk))
+		return PTR_ERR(clk);
+
+	port->uartclk = clk_get_rate(clk);
+	port->iotype = UPIO_MEM;
+	port->mapbase = res_mem->start;
+	port->irq = res_irq->start;
+	port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_LOW_LATENCY;
+	port->dev = &pdev->dev;
+	port->line = pdev->id;
+	port->type = PORT_MESON;
+	port->x_char = 0;
+	port->ops = &meson_uart_ops;
+	port->fifosize = 64;
+
+	meson_ports[pdev->id] = port;
+	platform_set_drvdata(pdev, port);
+
+	ret = uart_add_one_port(&meson_uart_driver, port);
+	if (ret)
+		meson_ports[pdev->id] = NULL;
+
+	return ret;
+}
+
+static int meson_uart_remove(struct platform_device *pdev)
+{
+	struct uart_port *port;
+
+	port = platform_get_drvdata(pdev);
+	uart_remove_one_port(&meson_uart_driver, port);
+	meson_ports[pdev->id] = NULL;
+
+	return 0;
+}
+
+
+static const struct of_device_id meson_uart_dt_match[] = {
+	{ .compatible = "amlogic,meson-uart" },
+	{ /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, meson_uart_dt_match);
+
+static  struct platform_driver meson_uart_platform_driver = {
+	.probe		= meson_uart_probe,
+	.remove		= meson_uart_remove,
+	.driver		= {
+		.owner		= THIS_MODULE,
+		.name		= "meson_uart",
+		.of_match_table	= meson_uart_dt_match,
+	},
+};
+
+static int __init meson_uart_init(void)
+{
+	int ret;
+
+	ret = uart_register_driver(&meson_uart_driver);
+	if (ret)
+		return ret;
+
+	ret = platform_driver_register(&meson_uart_platform_driver);
+	if (ret)
+		uart_unregister_driver(&meson_uart_driver);
+
+	return ret;
+}
+
+static void __exit meson_uart_exit(void)
+{
+	platform_driver_unregister(&meson_uart_platform_driver);
+	uart_unregister_driver(&meson_uart_driver);
+}
+
+module_init(meson_uart_init);
+module_exit(meson_uart_exit);
+
+MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
+MODULE_DESCRIPTION("Amlogic Meson serial port driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h
index 5820269..16ad852 100644
--- a/include/uapi/linux/serial_core.h
+++ b/include/uapi/linux/serial_core.h
@@ -244,4 +244,7 @@
 /* SC16IS74xx */
 #define PORT_SC16IS7XX   108
 
+/* MESON */
+#define PORT_MESON	109
+
 #endif /* _UAPILINUX_SERIAL_CORE_H */
-- 
1.9.1

Re: [PATCH 2/7] ARM: meson: serial: add MesonX SoC on-chip uart driver

[Carlo Caione]

On Sun, Aug 17, 2014 at 12:49:49PM +0200, Carlo Caione wrote:
> The SoC has four fully functional UARTs which use the same programming
> model. They are named UART_A, UART_B, UART_C and UART_AO (Always-On)
> which cannot be powered off.
> 
> Signed-off-by: Carlo Caione <carlo@caione.org>
> ---

<cut>

Hi,
Any feedback on this patch before submitting v2?

Thanks,

-- 
Carlo Caione

Re: [PATCH 2/7] ARM: meson: serial: add MesonX SoC on-chip uart driver

[Carlo Caione]

On dom, ago 17, 2014 at 12:49:49 +0200, Carlo Caione wrote:
> The SoC has four fully functional UARTs which use the same programming
> model. They are named UART_A, UART_B, UART_C and UART_AO (Always-On)
> which cannot be powered off.
> 
> Signed-off-by: Carlo Caione <carlo@caione.org>
> ---

Ping

-- 
Carlo Caione

Re: [PATCH 2/7] ARM: meson: serial: add MesonX SoC on-chip uart driver

[Greg KH]

On Sat, Sep 06, 2014 at 08:28:04PM +0200, Carlo Caione wrote:
> On dom, ago 17, 2014 at 12:49:49 +0200, Carlo Caione wrote:
> > The SoC has four fully functional UARTs which use the same programming
> > model. They are named UART_A, UART_B, UART_C and UART_AO (Always-On)
> > which cannot be powered off.
> > 
> > Signed-off-by: Carlo Caione <carlo@caione.org>
> > ---
> 
> Ping

It's still in my queue, sorry, been busy with conferences and the like,
should get to everything next week...

greg k-h

Re: [PATCH 2/7] ARM: meson: serial: add MesonX SoC on-chip uart driver

[Carlo Caione]

On sab, set 06, 2014 at 11:38:34 -0700, Greg KH wrote:
> On Sat, Sep 06, 2014 at 08:28:04PM +0200, Carlo Caione wrote:
> > On dom, ago 17, 2014 at 12:49:49 +0200, Carlo Caione wrote:
> > > The SoC has four fully functional UARTs which use the same programming
> > > model. They are named UART_A, UART_B, UART_C and UART_AO (Always-On)
> > > which cannot be powered off.
> > > 
> > > Signed-off-by: Carlo Caione <carlo@caione.org>
> > > ---
> > 
> > Ping
> 
> It's still in my queue, sorry, been busy with conferences and the like,
> should get to everything next week...

No prob. I'll wait, thanks.

-- 
Carlo Caione

[PATCH 3/7] ARM: meson6: clocksource: add Meson6 timer support

[Carlo Caione]

Meson6 SoCs are equipped with 5 32-bit timers, called TIMER_A, TIMER_B,
TIMER_C, TIMER_D and TIMER_E.

The driver is providing clocksource support for the 32-bit counter using
TIMER_E. Clockevents are also supported using TIMER_A.

Signed-off-by: Carlo Caione <carlo@caione.org>
---
 drivers/clocksource/Kconfig        |   3 +
 drivers/clocksource/Makefile       |   1 +
 drivers/clocksource/meson6_timer.c | 187 +++++++++++++++++++++++++++++++++++++
 3 files changed, 191 insertions(+)
 create mode 100644 drivers/clocksource/meson6_timer.c

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index cfd6519..38029ca 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -30,6 +30,9 @@ config ARMADA_370_XP_TIMER
 	bool
 	select CLKSRC_OF
 
+config MESON6_TIMER
+	bool
+
 config ORION_TIMER
 	select CLKSRC_OF
 	select CLKSRC_MMIO
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 7fd9fd1..e4ae987 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_ARCH_PRIMA2)	+= timer-prima2.o
 obj-$(CONFIG_ARCH_U300)		+= timer-u300.o
 obj-$(CONFIG_SUN4I_TIMER)	+= sun4i_timer.o
 obj-$(CONFIG_SUN5I_HSTIMER)	+= timer-sun5i.o
+obj-$(CONFIG_MESON6_TIMER)	+= meson6_timer.o
 obj-$(CONFIG_ARCH_TEGRA)	+= tegra20_timer.o
 obj-$(CONFIG_VT8500_TIMER)	+= vt8500_timer.o
 obj-$(CONFIG_ARCH_NSPIRE)	+= zevio-timer.o
diff --git a/drivers/clocksource/meson6_timer.c b/drivers/clocksource/meson6_timer.c
new file mode 100644
index 0000000..1ef1095
--- /dev/null
+++ b/drivers/clocksource/meson6_timer.c
@@ -0,0 +1,187 @@
+/*
+ * Amlogic Meson6 SoCs timer handling.
+ *
+ * Copyright (C) 2014 Carlo Caione
+ *
+ * Carlo Caione <carlo@caione.org>
+ *
+ * Based on code from Amlogic, Inc
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/irqreturn.h>
+#include <linux/sched_clock.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+enum {
+	A = 0,
+	B,
+	C,
+	D,
+};
+
+#define TIMER_ISA_MUX		0
+#define TIMER_ISA_E_VAL		0x14
+#define TIMER_ISA_t_VAL(t)	((t + 1) << 2)
+
+#define TIMER_t_INPUT_BIT(t)	(2 * t)
+#define TIMER_E_INPUT_BIT	8
+#define TIMER_t_INPUT_MASK(t)	(3UL << TIMER_t_INPUT_BIT(t))
+#define TIMER_E_INPUT_MASK	(7UL << TIMER_E_INPUT_BIT)
+#define TIMER_t_ENABLE_BIT(t)	(16 + t)
+#define TIMER_E_ENABLE_BIT	20
+#define TIMER_t_PERIODIC_BIT(t)	(12 + t)
+
+#define TIMER_UNIT_1us		0
+#define TIMER_E_UNIT_1us	1
+
+static void __iomem *timer_base;
+
+static cycle_t cycle_read_timer_e(struct clocksource *cs)
+{
+	return (cycle_t)readl(timer_base + TIMER_ISA_E_VAL);
+}
+
+static struct clocksource clocksource_timer_e = {
+	.name	= "meson6_timerE",
+	.rating	= 300,
+	.read	= cycle_read_timer_e,
+	.mask	= CLOCKSOURCE_MASK(32),
+	.flags  = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static u64 notrace meson6_timer_sched_read(void)
+{
+	return (u64)readl(timer_base + TIMER_ISA_E_VAL);
+}
+
+static void meson6_clkevt_time_stop(unsigned char timer)
+{
+	u32 val = readl(timer_base + TIMER_ISA_MUX);
+
+	writel(val & ~TIMER_t_ENABLE_BIT(timer), timer_base + TIMER_ISA_MUX);
+}
+
+static void meson6_clkevt_time_setup(unsigned char timer, unsigned long delay)
+{
+	writel(delay, timer_base + TIMER_ISA_t_VAL(timer));
+}
+
+static void meson6_clkevt_time_start(unsigned char timer, bool periodic)
+{
+	u32 val = readl(timer_base + TIMER_ISA_MUX);
+
+	if (periodic)
+		val |= TIMER_t_PERIODIC_BIT(timer);
+	else
+		val &= ~TIMER_t_PERIODIC_BIT(timer);
+
+	writel(val | TIMER_t_ENABLE_BIT(timer), timer_base + TIMER_ISA_MUX);
+}
+
+static void meson6_clkevt_mode(enum clock_event_mode mode,
+			       struct clock_event_device *clk)
+{
+	switch (mode) {
+	case CLOCK_EVT_MODE_PERIODIC:
+		meson6_clkevt_time_stop(A);
+		meson6_clkevt_time_setup(A, USEC_PER_SEC/HZ - 1);
+		meson6_clkevt_time_start(A, true);
+		break;
+	case CLOCK_EVT_MODE_ONESHOT:
+		meson6_clkevt_time_stop(A);
+		meson6_clkevt_time_start(A, false);
+		break;
+	case CLOCK_EVT_MODE_UNUSED:
+	case CLOCK_EVT_MODE_SHUTDOWN:
+	default:
+		meson6_clkevt_time_stop(A);
+		break;
+	}
+}
+
+static int meson6_clkevt_next_event(unsigned long evt,
+				    struct clock_event_device *unused)
+{
+	meson6_clkevt_time_stop(A);
+	meson6_clkevt_time_setup(A, evt);
+	meson6_clkevt_time_start(A, false);
+
+	return 0;
+}
+
+static struct clock_event_device meson6_clockevent = {
+	.name		= "meson6_tick",
+	.rating		= 400,
+	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+	.set_mode	= meson6_clkevt_mode,
+	.set_next_event	= meson6_clkevt_next_event,
+};
+
+static irqreturn_t meson6_timer_interrupt(int irq, void *dev_id)
+{
+	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
+
+	evt->event_handler(evt);
+
+	return IRQ_HANDLED;
+}
+
+static struct irqaction meson6_timer_irq = {
+	.name		= "meson6_timerA",
+	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
+	.handler	= meson6_timer_interrupt,
+	.dev_id		= &meson6_clockevent,
+};
+
+static void __init meson6_timer_init(struct device_node *node)
+{
+	u32 val;
+	int ret, irq;
+
+	timer_base = of_iomap(node, 0);
+	if (!timer_base)
+		panic("Can't map registers");
+
+	irq = irq_of_parse_and_map(node, 0);
+	if (irq <= 0)
+		panic("Can't parse IRQ");
+
+	/* Set 1us for timer E */
+	val = readl(timer_base + TIMER_ISA_MUX);
+	val &= ~TIMER_E_INPUT_MASK;
+	val |= TIMER_E_UNIT_1us << TIMER_E_INPUT_BIT;
+	writel(val, timer_base + TIMER_ISA_MUX);
+
+	sched_clock_register(meson6_timer_sched_read, 32, USEC_PER_SEC);
+	clocksource_register_khz(&clocksource_timer_e, 1000);
+
+	/* Timer A base 1us */
+	val &= ~TIMER_t_INPUT_MASK(A);
+	val |= TIMER_UNIT_1us << TIMER_t_INPUT_BIT(A);
+	writel(val, timer_base + TIMER_ISA_MUX);
+
+	/* Stop the timer A */
+	meson6_clkevt_time_stop(A);
+
+	ret = setup_irq(irq, &meson6_timer_irq);
+	if (ret)
+		pr_warn("failed to setup irq %d\n", irq);
+
+	meson6_clockevent.cpumask = cpu_possible_mask;
+	meson6_clockevent.irq = irq;
+
+	clockevents_config_and_register(&meson6_clockevent, USEC_PER_SEC,
+					1, 0xfffe);
+}
+CLOCKSOURCE_OF_DECLARE(meson6, "amlogic,meson6-timer",
+		       meson6_timer_init);
-- 
1.9.1

Re: [PATCH 3/7] ARM: meson6: clocksource: add Meson6 timer support

[Matthias Brugger]

On 17/08/14 12:49, Carlo Caione wrote:
> Meson6 SoCs are equipped with 5 32-bit timers, called TIMER_A, TIMER_B,
> TIMER_C, TIMER_D and TIMER_E.
>
> The driver is providing clocksource support for the 32-bit counter using
> TIMER_E. Clockevents are also supported using TIMER_A.
>
> Signed-off-by: Carlo Caione <carlo@caione.org>
> ---
>   drivers/clocksource/Kconfig        |   3 +
>   drivers/clocksource/Makefile       |   1 +
>   drivers/clocksource/meson6_timer.c | 187 +++++++++++++++++++++++++++++++++++++
>   3 files changed, 191 insertions(+)
>   create mode 100644 drivers/clocksource/meson6_timer.c
>
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index cfd6519..38029ca 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -30,6 +30,9 @@ config ARMADA_370_XP_TIMER
>   	bool
>   	select CLKSRC_OF
>
> +config MESON6_TIMER
> +	bool
> +
>   config ORION_TIMER
>   	select CLKSRC_OF
>   	select CLKSRC_MMIO
> diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
> index 7fd9fd1..e4ae987 100644
> --- a/drivers/clocksource/Makefile
> +++ b/drivers/clocksource/Makefile
> @@ -25,6 +25,7 @@ obj-$(CONFIG_ARCH_PRIMA2)	+= timer-prima2.o
>   obj-$(CONFIG_ARCH_U300)		+= timer-u300.o
>   obj-$(CONFIG_SUN4I_TIMER)	+= sun4i_timer.o
>   obj-$(CONFIG_SUN5I_HSTIMER)	+= timer-sun5i.o
> +obj-$(CONFIG_MESON6_TIMER)	+= meson6_timer.o
>   obj-$(CONFIG_ARCH_TEGRA)	+= tegra20_timer.o
>   obj-$(CONFIG_VT8500_TIMER)	+= vt8500_timer.o
>   obj-$(CONFIG_ARCH_NSPIRE)	+= zevio-timer.o
> diff --git a/drivers/clocksource/meson6_timer.c b/drivers/clocksource/meson6_timer.c
> new file mode 100644
> index 0000000..1ef1095
> --- /dev/null
> +++ b/drivers/clocksource/meson6_timer.c
> @@ -0,0 +1,187 @@
> +/*
> + * Amlogic Meson6 SoCs timer handling.
> + *
> + * Copyright (C) 2014 Carlo Caione
> + *
> + * Carlo Caione <carlo@caione.org>
> + *
> + * Based on code from Amlogic, Inc
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clockchips.h>
> +#include <linux/interrupt.h>
> +#include <linux/irq.h>
> +#include <linux/irqreturn.h>
> +#include <linux/sched_clock.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +
> +enum {
> +	A = 0,
> +	B,
> +	C,
> +	D,
> +};

You are just using timer A, so this enum is unnecessary. Please use a 
define instead. Also it would be better, if the define would be 
explenatory then just the letter 'A'.

> +
> +#define TIMER_ISA_MUX		0
> +#define TIMER_ISA_E_VAL		0x14
> +#define TIMER_ISA_t_VAL(t)	((t + 1) << 2)
> +
> +#define TIMER_t_INPUT_BIT(t)	(2 * t)

Please put braces around 't'.

> +#define TIMER_E_INPUT_BIT	8

 From the enum above, missing timer E would be 4 so you can use the 
TIMER_t_INPUT_BIT(t) macro, right?

> +#define TIMER_t_INPUT_MASK(t)	(3UL << TIMER_t_INPUT_BIT(t))
> +#define TIMER_E_INPUT_MASK	(7UL << TIMER_E_INPUT_BIT)
> +#define TIMER_t_ENABLE_BIT(t)	(16 + t)
> +#define TIMER_E_ENABLE_BIT	20
> +#define TIMER_t_PERIODIC_BIT(t)	(12 + t)

Please put braces around 't'.

> +
> +#define TIMER_UNIT_1us		0
> +#define TIMER_E_UNIT_1us	1

Please don't use lower case characters in defines.

> +
> +static void __iomem *timer_base;
> +
> +static cycle_t cycle_read_timer_e(struct clocksource *cs)
> +{
> +	return (cycle_t)readl(timer_base + TIMER_ISA_E_VAL);
> +}
> +
> +static struct clocksource clocksource_timer_e = {
> +	.name	= "meson6_timerE",
> +	.rating	= 300,
> +	.read	= cycle_read_timer_e,
> +	.mask	= CLOCKSOURCE_MASK(32),
> +	.flags  = CLOCK_SOURCE_IS_CONTINUOUS,
> +};
> +
> +static u64 notrace meson6_timer_sched_read(void)
> +{
> +	return (u64)readl(timer_base + TIMER_ISA_E_VAL);
> +}
> +
> +static void meson6_clkevt_time_stop(unsigned char timer)
> +{
> +	u32 val = readl(timer_base + TIMER_ISA_MUX);
> +
> +	writel(val & ~TIMER_t_ENABLE_BIT(timer), timer_base + TIMER_ISA_MUX);
> +}
> +
> +static void meson6_clkevt_time_setup(unsigned char timer, unsigned long delay)
> +{
> +	writel(delay, timer_base + TIMER_ISA_t_VAL(timer));
> +}
> +
> +static void meson6_clkevt_time_start(unsigned char timer, bool periodic)
> +{
> +	u32 val = readl(timer_base + TIMER_ISA_MUX);
> +
> +	if (periodic)
> +		val |= TIMER_t_PERIODIC_BIT(timer);
> +	else
> +		val &= ~TIMER_t_PERIODIC_BIT(timer);
> +
> +	writel(val | TIMER_t_ENABLE_BIT(timer), timer_base + TIMER_ISA_MUX);
> +}
> +
> +static void meson6_clkevt_mode(enum clock_event_mode mode,
> +			       struct clock_event_device *clk)
> +{
> +	switch (mode) {
> +	case CLOCK_EVT_MODE_PERIODIC:
> +		meson6_clkevt_time_stop(A);
> +		meson6_clkevt_time_setup(A, USEC_PER_SEC/HZ - 1);
> +		meson6_clkevt_time_start(A, true);
> +		break;
> +	case CLOCK_EVT_MODE_ONESHOT:
> +		meson6_clkevt_time_stop(A);
> +		meson6_clkevt_time_start(A, false);
> +		break;
> +	case CLOCK_EVT_MODE_UNUSED:
> +	case CLOCK_EVT_MODE_SHUTDOWN:
> +	default:
> +		meson6_clkevt_time_stop(A);
> +		break;
> +	}
> +}
> +
> +static int meson6_clkevt_next_event(unsigned long evt,
> +				    struct clock_event_device *unused)
> +{
> +	meson6_clkevt_time_stop(A);
> +	meson6_clkevt_time_setup(A, evt);
> +	meson6_clkevt_time_start(A, false);
> +
> +	return 0;
> +}
> +
> +static struct clock_event_device meson6_clockevent = {
> +	.name		= "meson6_tick",
> +	.rating		= 400,
> +	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
> +	.set_mode	= meson6_clkevt_mode,
> +	.set_next_event	= meson6_clkevt_next_event,
> +};
> +
> +static irqreturn_t meson6_timer_interrupt(int irq, void *dev_id)
> +{
> +	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
> +
> +	evt->event_handler(evt);
> +
> +	return IRQ_HANDLED;
> +}
> +
> +static struct irqaction meson6_timer_irq = {
> +	.name		= "meson6_timerA",
> +	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
> +	.handler	= meson6_timer_interrupt,
> +	.dev_id		= &meson6_clockevent,
> +};
> +
> +static void __init meson6_timer_init(struct device_node *node)
> +{
> +	u32 val;
> +	int ret, irq;
> +
> +	timer_base = of_iomap(node, 0);

Please use of_io_request_and_map instead.

> +	if (!timer_base)
> +		panic("Can't map registers");
> +
> +	irq = irq_of_parse_and_map(node, 0);
> +	if (irq <= 0)
> +		panic("Can't parse IRQ");
> +
> +	/* Set 1us for timer E */
> +	val = readl(timer_base + TIMER_ISA_MUX);
> +	val &= ~TIMER_E_INPUT_MASK;
> +	val |= TIMER_E_UNIT_1us << TIMER_E_INPUT_BIT;
> +	writel(val, timer_base + TIMER_ISA_MUX);
> +
> +	sched_clock_register(meson6_timer_sched_read, 32, USEC_PER_SEC);
> +	clocksource_register_khz(&clocksource_timer_e, 1000);

Why don't you use clocksource_mmio_init?

> +
> +	/* Timer A base 1us */
> +	val &= ~TIMER_t_INPUT_MASK(A);
> +	val |= TIMER_UNIT_1us << TIMER_t_INPUT_BIT(A);
> +	writel(val, timer_base + TIMER_ISA_MUX);

Is this dependant on any clocking of the timer?

> +
> +	/* Stop the timer A */
> +	meson6_clkevt_time_stop(A);
> +
> +	ret = setup_irq(irq, &meson6_timer_irq);
> +	if (ret)
> +		pr_warn("failed to setup irq %d\n", irq);
> +
> +	meson6_clockevent.cpumask = cpu_possible_mask;
> +	meson6_clockevent.irq = irq;
> +
> +	clockevents_config_and_register(&meson6_clockevent, USEC_PER_SEC,
> +					1, 0xfffe);
> +}
> +CLOCKSOURCE_OF_DECLARE(meson6, "amlogic,meson6-timer",
> +		       meson6_timer_init);
>

Re: [PATCH 3/7] ARM: meson6: clocksource: add Meson6 timer support

[Carlo Caione]

On Mon, Aug 18, 2014 at 01:59:38PM +0200, Matthias Brugger wrote:
> On 17/08/14 12:49, Carlo Caione wrote:
> >+enum {
> >+	A = 0,
> >+	B,
> >+	C,
> >+	D,
> >+};
> 
> You are just using timer A, so this enum is unnecessary. Please use
> a define instead. Also it would be better, if the define would be
> explenatory then just the letter 'A'.

In the meson6 SoCs there are 4 timers (TIMERA, TIMERB, TIMERC and
TIMERD). From the source code released by Amlogic it seems that they
have exactly the same characteristics and any of them can be used for
the clockevents. So either I fix the usage of only the TIMERA in the
driver or use the DTS to specify which one to use.

> >+
> >+#define TIMER_ISA_MUX		0
> >+#define TIMER_ISA_E_VAL		0x14
> >+#define TIMER_ISA_t_VAL(t)	((t + 1) << 2)
> >+
> >+#define TIMER_t_INPUT_BIT(t)	(2 * t)
> 
> Please put braces around 't'.

Ok

> >+#define TIMER_E_INPUT_BIT	8
> 
> From the enum above, missing timer E would be 4 so you can use the
> TIMER_t_INPUT_BIT(t) macro, right?

Right. It was to be consistent since the mask for TIMERE is different.
But I'll fix it.

> >+#define TIMER_t_INPUT_MASK(t)	(3UL << TIMER_t_INPUT_BIT(t))
> >+#define TIMER_E_INPUT_MASK	(7UL << TIMER_E_INPUT_BIT)
> >+#define TIMER_t_ENABLE_BIT(t)	(16 + t)
> >+#define TIMER_E_ENABLE_BIT	20
> >+#define TIMER_t_PERIODIC_BIT(t)	(12 + t)
> 
> Please put braces around 't'.

I'll do

> >+
> >+#define TIMER_UNIT_1us		0
> >+#define TIMER_E_UNIT_1us	1
> 
> Please don't use lower case characters in defines.

Ok

<cut>

> >+static void __init meson6_timer_init(struct device_node *node)
> >+{
> >+	u32 val;
> >+	int ret, irq;
> >+
> >+	timer_base = of_iomap(node, 0);
> 
> Please use of_io_request_and_map instead.

Agree. Fix in v2.

> >+	if (!timer_base)
> >+		panic("Can't map registers");
> >+
> >+	irq = irq_of_parse_and_map(node, 0);
> >+	if (irq <= 0)
> >+		panic("Can't parse IRQ");
> >+
> >+	/* Set 1us for timer E */
> >+	val = readl(timer_base + TIMER_ISA_MUX);
> >+	val &= ~TIMER_E_INPUT_MASK;
> >+	val |= TIMER_E_UNIT_1us << TIMER_E_INPUT_BIT;
> >+	writel(val, timer_base + TIMER_ISA_MUX);
> >+
> >+	sched_clock_register(meson6_timer_sched_read, 32, USEC_PER_SEC);
> >+	clocksource_register_khz(&clocksource_timer_e, 1000);
> 
> Why don't you use clocksource_mmio_init?

No real reason, I just missed that one.

> >+
> >+	/* Timer A base 1us */
> >+	val &= ~TIMER_t_INPUT_MASK(A);
> >+	val |= TIMER_UNIT_1us << TIMER_t_INPUT_BIT(A);
> >+	writel(val, timer_base + TIMER_ISA_MUX);
> 
> Is this dependant on any clocking of the timer?

No. At least this is what I can infer from the messy source code released by
Amlogic. I wish I had any documentation for these SoCs.

Thank you for your review,
 
-- 
Carlo Caione

Re: [PATCH 3/7] ARM: meson6: clocksource: add Meson6 timer support

[Mark Rutland]

On Sun, Aug 17, 2014 at 11:49:50AM +0100, Carlo Caione wrote:
> Meson6 SoCs are equipped with 5 32-bit timers, called TIMER_A, TIMER_B,
> TIMER_C, TIMER_D and TIMER_E.
> 
> The driver is providing clocksource support for the 32-bit counter using
> TIMER_E. Clockevents are also supported using TIMER_A.
> 
> Signed-off-by: Carlo Caione <carlo@caione.org>
> ---
>  drivers/clocksource/Kconfig        |   3 +
>  drivers/clocksource/Makefile       |   1 +
>  drivers/clocksource/meson6_timer.c | 187 +++++++++++++++++++++++++++++++++++++
>  3 files changed, 191 insertions(+)
>  create mode 100644 drivers/clocksource/meson6_timer.c
> 
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index cfd6519..38029ca 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -30,6 +30,9 @@ config ARMADA_370_XP_TIMER
>  	bool
>  	select CLKSRC_OF
>  
> +config MESON6_TIMER
> +	bool
> +
>  config ORION_TIMER
>  	select CLKSRC_OF
>  	select CLKSRC_MMIO
> diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
> index 7fd9fd1..e4ae987 100644
> --- a/drivers/clocksource/Makefile
> +++ b/drivers/clocksource/Makefile
> @@ -25,6 +25,7 @@ obj-$(CONFIG_ARCH_PRIMA2)	+= timer-prima2.o
>  obj-$(CONFIG_ARCH_U300)		+= timer-u300.o
>  obj-$(CONFIG_SUN4I_TIMER)	+= sun4i_timer.o
>  obj-$(CONFIG_SUN5I_HSTIMER)	+= timer-sun5i.o
> +obj-$(CONFIG_MESON6_TIMER)	+= meson6_timer.o
>  obj-$(CONFIG_ARCH_TEGRA)	+= tegra20_timer.o
>  obj-$(CONFIG_VT8500_TIMER)	+= vt8500_timer.o
>  obj-$(CONFIG_ARCH_NSPIRE)	+= zevio-timer.o
> diff --git a/drivers/clocksource/meson6_timer.c b/drivers/clocksource/meson6_timer.c
> new file mode 100644
> index 0000000..1ef1095
> --- /dev/null
> +++ b/drivers/clocksource/meson6_timer.c
> @@ -0,0 +1,187 @@
> +/*
> + * Amlogic Meson6 SoCs timer handling.
> + *
> + * Copyright (C) 2014 Carlo Caione
> + *
> + * Carlo Caione <carlo@caione.org>
> + *
> + * Based on code from Amlogic, Inc
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clockchips.h>
> +#include <linux/interrupt.h>
> +#include <linux/irq.h>
> +#include <linux/irqreturn.h>
> +#include <linux/sched_clock.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +
> +enum {
> +	A = 0,
> +	B,
> +	C,
> +	D,
> +};

That's a very terse set of enum names. I would recomment something a
little longer.

Any reason for missing E?

> +
> +#define TIMER_ISA_MUX		0
> +#define TIMER_ISA_E_VAL		0x14
> +#define TIMER_ISA_t_VAL(t)	((t + 1) << 2)
> +
> +#define TIMER_t_INPUT_BIT(t)	(2 * t)
> +#define TIMER_E_INPUT_BIT	8
> +#define TIMER_t_INPUT_MASK(t)	(3UL << TIMER_t_INPUT_BIT(t))
> +#define TIMER_E_INPUT_MASK	(7UL << TIMER_E_INPUT_BIT)
> +#define TIMER_t_ENABLE_BIT(t)	(16 + t)
> +#define TIMER_E_ENABLE_BIT	20
> +#define TIMER_t_PERIODIC_BIT(t)	(12 + t)

While I don't think it matters for any of these, it's usually good
practice to add parentheses around arguments, e.g.

#define FOO(x)		((x) * 2)

So you can avoid bad expansions in cases like:

FOO(reg + 4)

> +
> +#define TIMER_UNIT_1us		0
> +#define TIMER_E_UNIT_1us	1
> +
> +static void __iomem *timer_base;
> +
> +static cycle_t cycle_read_timer_e(struct clocksource *cs)
> +{
> +	return (cycle_t)readl(timer_base + TIMER_ISA_E_VAL);
> +}
> +
> +static struct clocksource clocksource_timer_e = {
> +	.name	= "meson6_timerE",

Do we really care which specific timer we're using within the block?

Why not just "meson6_clocksource"?

> +	.rating	= 300,
> +	.read	= cycle_read_timer_e,
> +	.mask	= CLOCKSOURCE_MASK(32),
> +	.flags  = CLOCK_SOURCE_IS_CONTINUOUS,
> +};

[...]

> +static irqreturn_t meson6_timer_interrupt(int irq, void *dev_id)
> +{
> +	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
> +
> +	evt->event_handler(evt);
> +
> +	return IRQ_HANDLED;
> +}
> +
> +static struct irqaction meson6_timer_irq = {
> +	.name		= "meson6_timerA",

Similarly to the clocksource naming, this might be better as
"meson6_timer", without the 'A'.

Thanks,
Mark.

Re: [PATCH 3/7] ARM: meson6: clocksource: add Meson6 timer support

[Carlo Caione]

On lun, ago 18, 2014 at 05:27:26 +0100, Mark Rutland wrote:
> On Sun, Aug 17, 2014 at 11:49:50AM +0100, Carlo Caione wrote:
> > +enum {
> > +	A = 0,
> > +	B,
> > +	C,
> > +	D,
> > +};
> 
> That's a very terse set of enum names. I would recomment something a
> little longer.
> 
> Any reason for missing E?

TIMER_E is a slightly different timer so I preferred to leave it apart.

> > +#define TIMER_ISA_MUX		0
> > +#define TIMER_ISA_E_VAL		0x14
> > +#define TIMER_ISA_t_VAL(t)	((t + 1) << 2)
> > +
> > +#define TIMER_t_INPUT_BIT(t)	(2 * t)
> > +#define TIMER_E_INPUT_BIT	8
> > +#define TIMER_t_INPUT_MASK(t)	(3UL << TIMER_t_INPUT_BIT(t))
> > +#define TIMER_E_INPUT_MASK	(7UL << TIMER_E_INPUT_BIT)
> > +#define TIMER_t_ENABLE_BIT(t)	(16 + t)
> > +#define TIMER_E_ENABLE_BIT	20
> > +#define TIMER_t_PERIODIC_BIT(t)	(12 + t)
> 
> While I don't think it matters for any of these, it's usually good
> practice to add parentheses around arguments, e.g.
> 
> #define FOO(x)		((x) * 2)
> 
> So you can avoid bad expansions in cases like:
> 
> FOO(reg + 4)

Agree. I'll change it.

> > +
> > +#define TIMER_UNIT_1us		0
> > +#define TIMER_E_UNIT_1us	1
> > +
> > +static void __iomem *timer_base;
> > +
> > +static cycle_t cycle_read_timer_e(struct clocksource *cs)
> > +{
> > +	return (cycle_t)readl(timer_base + TIMER_ISA_E_VAL);
> > +}
> > +
> > +static struct clocksource clocksource_timer_e = {
> > +	.name	= "meson6_timerE",
> 
> Do we really care which specific timer we're using within the block?
> 
> Why not just "meson6_clocksource"?

Just a reminder of which timer we are using. I'll fix it.

> > +	.rating	= 300,
> > +	.read	= cycle_read_timer_e,
> > +	.mask	= CLOCKSOURCE_MASK(32),
> > +	.flags  = CLOCK_SOURCE_IS_CONTINUOUS,
> > +};
> 
> [...]
> 
> > +static irqreturn_t meson6_timer_interrupt(int irq, void *dev_id)
> > +{
> > +	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
> > +
> > +	evt->event_handler(evt);
> > +
> > +	return IRQ_HANDLED;
> > +}
> > +
> > +static struct irqaction meson6_timer_irq = {
> > +	.name		= "meson6_timerA",
> 
> Similarly to the clocksource naming, this might be better as
> "meson6_timer", without the 'A'.

Yep.

Thanks for the review,

-- 
Carlo Caione

[PATCH 4/7] ARM: meson: add basic support for MesonX SoCs

[Carlo Caione]

Signed-off-by: Carlo Caione <carlo@caione.org>
---
 arch/arm/Kconfig             |  2 ++
 arch/arm/Makefile            |  1 +
 arch/arm/mach-meson/Kconfig  | 13 +++++++++++++
 arch/arm/mach-meson/Makefile |  1 +
 arch/arm/mach-meson/meson.c  | 36 ++++++++++++++++++++++++++++++++++++
 5 files changed, 53 insertions(+)
 create mode 100644 arch/arm/mach-meson/Kconfig
 create mode 100644 arch/arm/mach-meson/Makefile
 create mode 100644 arch/arm/mach-meson/meson.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c49a775..cc52a8f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -888,6 +888,8 @@ source "arch/arm/mach-keystone/Kconfig"
 
 source "arch/arm/mach-ks8695/Kconfig"
 
+source "arch/arm/mach-meson/Kconfig"
+
 source "arch/arm/mach-msm/Kconfig"
 
 source "arch/arm/mach-moxart/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 0ce9d0f..320aa57 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -168,6 +168,7 @@ machine-$(CONFIG_ARCH_IXP4XX)		+= ixp4xx
 machine-$(CONFIG_ARCH_KEYSTONE)		+= keystone
 machine-$(CONFIG_ARCH_KS8695)		+= ks8695
 machine-$(CONFIG_ARCH_LPC32XX)		+= lpc32xx
+machine-$(CONFIG_ARCH_MESON)		+= meson
 machine-$(CONFIG_ARCH_MMP)		+= mmp
 machine-$(CONFIG_ARCH_MOXART)		+= moxart
 machine-$(CONFIG_ARCH_MSM)		+= msm
diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
new file mode 100644
index 0000000..2c1154e
--- /dev/null
+++ b/arch/arm/mach-meson/Kconfig
@@ -0,0 +1,13 @@
+menuconfig ARCH_MESON
+	bool "Amlogic Meson SoCs" if ARCH_MULTI_V7
+	select GENERIC_IRQ_CHIP
+	select ARM_GIC
+
+if ARCH_MESON
+
+config MACH_MESON6
+	bool "Amlogic Meson6 (8726MX) SoCs support"
+	default ARCH_MESON
+	select MESON6_TIMER
+
+endif
diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile
new file mode 100644
index 0000000..9d7380e
--- /dev/null
+++ b/arch/arm/mach-meson/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_ARCH_MESON) += meson.o
diff --git a/arch/arm/mach-meson/meson.c b/arch/arm/mach-meson/meson.c
new file mode 100644
index 0000000..4528312
--- /dev/null
+++ b/arch/arm/mach-meson/meson.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2014 Carlo Caione <carlo@caione.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+
+static __init void meson_init_machine_devicetree(void)
+{
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char * const m6_common_board_compat[] = {
+	"amlogic,8726_mx",
+	"amlogic,8726_mxs",
+	"amlogic,8726_mxl",
+	"amlogic,meson6",
+	NULL,
+};
+
+DT_MACHINE_START(AML8726_MX, "Amlogic Meson6 platform")
+	.init_machine	= meson_init_machine_devicetree,
+	.dt_compat	= m6_common_board_compat,
+MACHINE_END
+
-- 
1.9.1

Re: [PATCH 4/7] ARM: meson: add basic support for MesonX SoCs

[Maxime Ripard]

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Hi Carlo,

On Sun, Aug 17, 2014 at 12:49:51PM +0200, Carlo Caione wrote:
> Signed-off-by: Carlo Caione <carlo@caione.org>

A commit log would be nice

> ---
>  arch/arm/Kconfig             |  2 ++
>  arch/arm/Makefile            |  1 +
>  arch/arm/mach-meson/Kconfig  | 13 +++++++++++++
>  arch/arm/mach-meson/Makefile |  1 +
>  arch/arm/mach-meson/meson.c  | 36 ++++++++++++++++++++++++++++++++++++
>  5 files changed, 53 insertions(+)
>  create mode 100644 arch/arm/mach-meson/Kconfig
>  create mode 100644 arch/arm/mach-meson/Makefile
>  create mode 100644 arch/arm/mach-meson/meson.c
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index c49a775..cc52a8f 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -888,6 +888,8 @@ source "arch/arm/mach-keystone/Kconfig"
>  
>  source "arch/arm/mach-ks8695/Kconfig"
>  
> +source "arch/arm/mach-meson/Kconfig"
> +
>  source "arch/arm/mach-msm/Kconfig"
>  
>  source "arch/arm/mach-moxart/Kconfig"
> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> index 0ce9d0f..320aa57 100644
> --- a/arch/arm/Makefile
> +++ b/arch/arm/Makefile
> @@ -168,6 +168,7 @@ machine-$(CONFIG_ARCH_IXP4XX)		+= ixp4xx
>  machine-$(CONFIG_ARCH_KEYSTONE)		+= keystone
>  machine-$(CONFIG_ARCH_KS8695)		+= ks8695
>  machine-$(CONFIG_ARCH_LPC32XX)		+= lpc32xx
> +machine-$(CONFIG_ARCH_MESON)		+= meson
>  machine-$(CONFIG_ARCH_MMP)		+= mmp
>  machine-$(CONFIG_ARCH_MOXART)		+= moxart
>  machine-$(CONFIG_ARCH_MSM)		+= msm
> diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
> new file mode 100644
> index 0000000..2c1154e
> --- /dev/null
> +++ b/arch/arm/mach-meson/Kconfig
> @@ -0,0 +1,13 @@
> +menuconfig ARCH_MESON
> +	bool "Amlogic Meson SoCs" if ARCH_MULTI_V7
> +	select GENERIC_IRQ_CHIP
> +	select ARM_GIC
> +
> +if ARCH_MESON
> +
> +config MACH_MESON6
> +	bool "Amlogic Meson6 (8726MX) SoCs support"
> +	default ARCH_MESON
> +	select MESON6_TIMER
> +
> +endif
> diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile
> new file mode 100644
> index 0000000..9d7380e
> --- /dev/null
> +++ b/arch/arm/mach-meson/Makefile
> @@ -0,0 +1 @@
> +obj-$(CONFIG_ARCH_MESON) += meson.o
> diff --git a/arch/arm/mach-meson/meson.c b/arch/arm/mach-meson/meson.c
> new file mode 100644
> index 0000000..4528312
> --- /dev/null
> +++ b/arch/arm/mach-meson/meson.c
> @@ -0,0 +1,36 @@
> +/*
> + * Copyright (C) 2014 Carlo Caione <carlo@caione.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + */
> +
> +#include <linux/of_platform.h>
> +#include <asm/mach/arch.h>
> +
> +static __init void meson_init_machine_devicetree(void)
> +{
> +	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
> +}

This is the default, you can just remove it

> +
> +static const char * const m6_common_board_compat[] = {
> +	"amlogic,8726_mx",
> +	"amlogic,8726_mxs",
> +	"amlogic,8726_mxl",
> +	"amlogic,meson6",

Why are all those compatibles needed? Usually, you add a single one
per SoC (which would be the last in your case I guess.

> +	NULL,
> +};
> +
> +DT_MACHINE_START(AML8726_MX, "Amlogic Meson6 platform")
> +	.init_machine	= meson_init_machine_devicetree,

And since you don't need the init machine, you can just use the
generic machine support. I'm not sure what's been decided on this,
should we remove such empty machines?

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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Re: [PATCH 4/7] ARM: meson: add basic support for MesonX SoCs

[Carlo Caione]

On Sun, Aug 17, 2014 at 04:21:15PM +0200, Maxime Ripard wrote:
> Hi Carlo,

Hi Maxime,
thank you for reviewing also these patches, I'll keep you in CC for the
next revisions if you are interested.

> > +static __init void meson_init_machine_devicetree(void)
> > +{
> > +	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
> > +}
> 
> This is the default, you can just remove it

Agree

> > +static const char * const m6_common_board_compat[] = {
> > +	"amlogic,8726_mx",
> > +	"amlogic,8726_mxs",
> > +	"amlogic,8726_mxl",
> > +	"amlogic,meson6",
> 
> Why are all those compatibles needed? Usually, you add a single one
> per SoC (which would be the last in your case I guess.

They are taken from the weird DTS in the original Amlogic sources but I
guess you are right. I am actually more inclined to just leave "8726_mx"
and "meson6" since online you can find equally both the versions for
exactly the same SoCs.

> > +	NULL,
> > +};
> > +
> > +DT_MACHINE_START(AML8726_MX, "Amlogic Meson6 platform")
> > +	.init_machine	= meson_init_machine_devicetree,
> 
> And since you don't need the init machine, you can just use the
> generic machine support. I'm not sure what's been decided on this,
> should we remove such empty machines?

I can get rid of the .init_machine but what about the .dt_compat field?

Thanks,

-- 
Carlo Caione

Re: [PATCH 4/7] ARM: meson: add basic support for MesonX SoCs

[Matthias Brugger]

2014-08-18 15:27 GMT+02:00 Carlo Caione <carlo@caione.org>:
> On Sun, Aug 17, 2014 at 04:21:15PM +0200, Maxime Ripard wrote:
>> Hi Carlo,
>
> Hi Maxime,
> thank you for reviewing also these patches, I'll keep you in CC for the
> next revisions if you are interested.
>
>> > +static __init void meson_init_machine_devicetree(void)
>> > +{
>> > +   of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
>> > +}
>>
>> This is the default, you can just remove it
>
> Agree
>
>> > +static const char * const m6_common_board_compat[] = {
>> > +   "amlogic,8726_mx",
>> > +   "amlogic,8726_mxs",
>> > +   "amlogic,8726_mxl",
>> > +   "amlogic,meson6",
>>
>> Why are all those compatibles needed? Usually, you add a single one
>> per SoC (which would be the last in your case I guess.
>
> They are taken from the weird DTS in the original Amlogic sources but I
> guess you are right. I am actually more inclined to just leave "8726_mx"
> and "meson6" since online you can find equally both the versions for
> exactly the same SoCs.
>
>> > +   NULL,
>> > +};
>> > +
>> > +DT_MACHINE_START(AML8726_MX, "Amlogic Meson6 platform")
>> > +   .init_machine   = meson_init_machine_devicetree,
>>
>> And since you don't need the init machine, you can just use the
>> generic machine support. I'm not sure what's been decided on this,
>> should we remove such empty machines?
>
> I can get rid of the .init_machine but what about the .dt_compat field?

AFIAK there is no consensus about that.
For now I would leave the .dt_compat field. There are proposals which
try to get rid of the name_str
in the DT_MACHINE_START [0], but from what I know they are not yet merged.

Cheers,
Matthias

[0] http://lists.infradead.org/pipermail/linux-arm-kernel/2013-November/208878.html

>
> Thanks,
>
> --
> Carlo Caione
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel



-- 
motzblog.wordpress.com

Re: [PATCH 4/7] ARM: meson: add basic support for MesonX SoCs

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 1820 bytes --]

Hi,

On Mon, Aug 18, 2014 at 03:27:13PM +0200, Carlo Caione wrote:
> On Sun, Aug 17, 2014 at 04:21:15PM +0200, Maxime Ripard wrote:
> > Hi Carlo,
> 
> Hi Maxime,
> thank you for reviewing also these patches, I'll keep you in CC for the
> next revisions if you are interested.

Yep, sure.

> > > +static const char * const m6_common_board_compat[] = {
> > > +	"amlogic,8726_mx",
> > > +	"amlogic,8726_mxs",
> > > +	"amlogic,8726_mxl",
> > > +	"amlogic,meson6",
> > 
> > Why are all those compatibles needed? Usually, you add a single one
> > per SoC (which would be the last in your case I guess.
> 
> They are taken from the weird DTS in the original Amlogic sources but I
> guess you are right. I am actually more inclined to just leave "8726_mx"
> and "meson6" since online you can find equally both the versions for
> exactly the same SoCs.

I don't really know what's the best option here, but you should really
choose one name and stick to it. Since the mach directory is called
meson, I guess meson6 would make more sense, but it's your call.

> > > +	NULL,
> > > +};
> > > +
> > > +DT_MACHINE_START(AML8726_MX, "Amlogic Meson6 platform")
> > > +	.init_machine	= meson_init_machine_devicetree,
> > 
> > And since you don't need the init machine, you can just use the
> > generic machine support. I'm not sure what's been decided on this,
> > should we remove such empty machines?
> 
> I can get rid of the .init_machine but what about the .dt_compat field?

Technically, it would work. The only drawbacks are that you don't get
the machine name in /proc/cpuinfo, and that you'll probably have to
add this file at some point in the future anyway.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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[PATCH 5/7] ARM: meson: dts: add basic Meson/Meson6/Meson6-atv1200 DTSI/DTS

[Carlo Caione]

The Meson6 SoC is produced by Amlogic inc. and it is based on 2 Cortex A9
and an ARM Mali-400 GPU.
This patch adds two basic DTSI for the preliminary support of Meson and
Meson6 SoCs. Another DTS is also added for supporting the atv1200 board,
produced by Geniatech inc.

Signed-off-by: Carlo Caione <carlo@caione.org>
---
 arch/arm/boot/dts/Makefile           |  1 +
 arch/arm/boot/dts/meson.dtsi         | 75 ++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/meson6-atv1200.dts | 27 +++++++++++++
 arch/arm/boot/dts/meson6.dtsi        | 44 +++++++++++++++++++++
 4 files changed, 147 insertions(+)
 create mode 100644 arch/arm/boot/dts/meson.dtsi
 create mode 100644 arch/arm/boot/dts/meson6-atv1200.dts
 create mode 100644 arch/arm/boot/dts/meson6.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b8c5cd3..604acce 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -159,6 +159,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \
 	kirkwood-ts419-6282.dtb
 dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
 dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
+dtb-$(CONFIG_MACH_MESON6) += meson6-atv1200.dtb
 dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb
 dtb-$(CONFIG_ARCH_MXC) += \
 	imx25-eukrea-mbimxsd25-baseboard.dtb \
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
new file mode 100644
index 0000000..934bb2c
--- /dev/null
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2014 Carlo Caione <carlo@caione.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	interrupt-parent = <&gic>;
+
+	aliases {
+		serial0 = &uart_AO;
+		serial1 = &uart_A;
+		serial2 = &uart_B;
+		serial3 = &uart_C;
+	};
+
+	gic: interrupt-controller@c4301000 {
+		compatible = "arm,cortex-a9-gic";
+		reg = <0xc4301000 0x1000>,
+		      <0xc4300100 0x0100>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+	};
+
+	timer@c1109940 {
+		compatible = "amlogic,meson6-timer";
+		reg = <0xc1109940 0x14>;
+		interrupts = <0 10 1>;
+	};
+
+	soc@c8100000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		uart_AO: serial@c81004c0 {
+			compatible = "amlogic,meson-uart";
+			reg = <0xc81004c0 0x14>;
+			interrupts = <0 90 1>;
+			clocks = <&clk81>;
+			status = "disabled";
+		};
+
+		uart_A: serial@c81084c0 {
+			compatible = "amlogic,meson-uart";
+			reg = <0xc81084c0 0x14>;
+			interrupts = <0 90 1>;
+			clocks = <&clk81>;
+			status = "disabled";
+		};
+
+		uart_B: serial@c81084dc {
+			compatible = "amlogic,meson-uart";
+			reg = <0xc81084dc 0x14>;
+			interrupts = <0 90 1>;
+			clocks = <&clk81>;
+			status = "disabled";
+		};
+
+		uart_C: serial@c8108700 {
+			compatible = "amlogic,meson-uart";
+			reg = <0xc8108700 0x14>;
+			interrupts = <0 90 1>;
+			clocks = <&clk81>;
+			status = "disabled";
+		};
+	};
+}; /* end of / */
+
diff --git a/arch/arm/boot/dts/meson6-atv1200.dts b/arch/arm/boot/dts/meson6-atv1200.dts
new file mode 100644
index 0000000..b358402
--- /dev/null
+++ b/arch/arm/boot/dts/meson6-atv1200.dts
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2014 Carlo Caione <carlo@caione.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+/include/ "meson6.dtsi"
+
+/ {
+	model = "Geniatech ATV1200";
+	compatible = "geniatech,atv1200";
+
+	memory {
+		reg = <0x40000000 0x80000000>;
+	};
+
+	soc@c8100000 {
+		uart_AO: serial@c81004c0 {
+			status = "okay";
+		};
+	};
+}; /* end of / */
+
diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi
new file mode 100644
index 0000000..d62add4
--- /dev/null
+++ b/arch/arm/boot/dts/meson6.dtsi
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2014 Carlo Caione <carlo@caione.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/include/ "meson.dtsi"
+
+/ {
+	model = "Amlogic Meson6 SoC";
+	compatible = "amlogic,meson6", "amlogic,8726_mx";
+
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <0x200>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <0x1>;
+		};
+	};
+
+	clocks {
+		#address-cells = <1>;
+
+		clk81: clk@0 {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <200000000>;
+		};
+	};
+}; /* end of / */
-- 
1.9.1

Re: [PATCH 5/7] ARM: meson: dts: add basic Meson/Meson6/Meson6-atv1200 DTSI/DTS

[Beniamino Galvani]

Hi,

On Sun, Aug 17, 2014 at 12:49:52PM +0200, Carlo Caione wrote:
> The Meson6 SoC is produced by Amlogic inc. and it is based on 2 Cortex A9
> and an ARM Mali-400 GPU.
> This patch adds two basic DTSI for the preliminary support of Meson and
> Meson6 SoCs. Another DTS is also added for supporting the atv1200 board,
> produced by Geniatech inc.
> index 0000000..d62add4
(...)
> --- /dev/null
> +++ b/arch/arm/boot/dts/meson6.dtsi
> @@ -0,0 +1,44 @@
> +/*
> + * Copyright 2014 Carlo Caione <carlo@caione.org>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +
> +/include/ "meson.dtsi"
> +
> +/ {
> +	model = "Amlogic Meson6 SoC";
> +	compatible = "amlogic,meson6", "amlogic,8726_mx";
> +
> +	interrupt-parent = <&gic>;
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu@0 {

The address after the @ should match the value of the 'reg' property.

> +			device_type = "cpu";
> +			compatible = "arm,cortex-a9";
> +			reg = <0x200>;
> +		};
> +
> +		cpu@1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a9";
> +			reg = <0x1>;

According to Documentation/devicetree/bindings/arm/cpus.txt, this
should be set to bits [23:0] of the CPU MPIDR register, in this case
0x201.

Beniamino

> +		};
> +	};
> +
> +	clocks {
> +		#address-cells = <1>;
> +
> +		clk81: clk@0 {
> +			#clock-cells = <0>;
> +			compatible = "fixed-clock";
> +			clock-frequency = <200000000>;
> +		};
> +	};
> +}; /* end of / */
> -- 
> 1.9.1
> 

Re: [PATCH 5/7] ARM: meson: dts: add basic Meson/Meson6/Meson6-atv1200 DTSI/DTS

[Carlo Caione]

On Sun, Aug 17, 2014 at 4:42 PM, Beniamino Galvani <b.galvani@gmail.com> wrote:
> Hi,

>> +/include/ "meson.dtsi"
>> +
>> +/ {
>> +     model = "Amlogic Meson6 SoC";
>> +     compatible = "amlogic,meson6", "amlogic,8726_mx";
>> +
>> +     interrupt-parent = <&gic>;
>> +
>> +     cpus {
>> +             #address-cells = <1>;
>> +             #size-cells = <0>;
>> +
>> +             cpu@0 {
>
> The address after the @ should match the value of the 'reg' property.

Agree

>> +                     device_type = "cpu";
>> +                     compatible = "arm,cortex-a9";
>> +                     reg = <0x200>;
>> +             };
>> +
>> +             cpu@1 {
>> +                     device_type = "cpu";
>> +                     compatible = "arm,cortex-a9";
>> +                     reg = <0x1>;
>
> According to Documentation/devicetree/bindings/arm/cpus.txt, this
> should be set to bits [23:0] of the CPU MPIDR register, in this case
> 0x201.

Right. Thanks for noticing.
I will fix it in v2.

Thank you,

-- 
Carlo Caione

Re: [PATCH 5/7] ARM: meson: dts: add basic Meson/Meson6/Meson6-atv1200 DTSI/DTS

[Mark Rutland]

On Sun, Aug 17, 2014 at 04:21:23PM +0100, Carlo Caione wrote:
> On Sun, Aug 17, 2014 at 4:42 PM, Beniamino Galvani <b.galvani@gmail.com> wrote:
> > Hi,
> 
> >> +/include/ "meson.dtsi"
> >> +
> >> +/ {
> >> +     model = "Amlogic Meson6 SoC";
> >> +     compatible = "amlogic,meson6", "amlogic,8726_mx";
> >> +
> >> +     interrupt-parent = <&gic>;
> >> +
> >> +     cpus {
> >> +             #address-cells = <1>;
> >> +             #size-cells = <0>;
> >> +
> >> +             cpu@0 {
> >
> > The address after the @ should match the value of the 'reg' property.

Just remember to strip the leading "0x" (this should be "cpu@200").

Cheers,
Mark.

Re: [PATCH 5/7] ARM: meson: dts: add basic Meson/Meson6/Meson6-atv1200 DTSI/DTS

[Mark Rutland]

On Sun, Aug 17, 2014 at 11:49:52AM +0100, Carlo Caione wrote:
> The Meson6 SoC is produced by Amlogic inc. and it is based on 2 Cortex A9
> and an ARM Mali-400 GPU.
> This patch adds two basic DTSI for the preliminary support of Meson and
> Meson6 SoCs. Another DTS is also added for supporting the atv1200 board,
> produced by Geniatech inc.
> 
> Signed-off-by: Carlo Caione <carlo@caione.org>
> ---
>  arch/arm/boot/dts/Makefile           |  1 +
>  arch/arm/boot/dts/meson.dtsi         | 75 ++++++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/meson6-atv1200.dts | 27 +++++++++++++
>  arch/arm/boot/dts/meson6.dtsi        | 44 +++++++++++++++++++++
>  4 files changed, 147 insertions(+)
>  create mode 100644 arch/arm/boot/dts/meson.dtsi
>  create mode 100644 arch/arm/boot/dts/meson6-atv1200.dts
>  create mode 100644 arch/arm/boot/dts/meson6.dtsi
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index b8c5cd3..604acce 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -159,6 +159,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \
>  	kirkwood-ts419-6282.dtb
>  dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
>  dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
> +dtb-$(CONFIG_MACH_MESON6) += meson6-atv1200.dtb
>  dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb
>  dtb-$(CONFIG_ARCH_MXC) += \
>  	imx25-eukrea-mbimxsd25-baseboard.dtb \
> diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
> new file mode 100644
> index 0000000..934bb2c
> --- /dev/null
> +++ b/arch/arm/boot/dts/meson.dtsi
> @@ -0,0 +1,75 @@
> +/*
> + * Copyright 2014 Carlo Caione <carlo@caione.org>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +
> +/include/ "skeleton.dtsi"
> +
> +/ {
> +	interrupt-parent = <&gic>;
> +
> +	aliases {
> +		serial0 = &uart_AO;
> +		serial1 = &uart_A;
> +		serial2 = &uart_B;
> +		serial3 = &uart_C;
> +	};
> +
> +	gic: interrupt-controller@c4301000 {
> +		compatible = "arm,cortex-a9-gic";
> +		reg = <0xc4301000 0x1000>,
> +		      <0xc4300100 0x0100>;
> +		interrupt-controller;
> +		#interrupt-cells = <3>;
> +	};
> +
> +	timer@c1109940 {
> +		compatible = "amlogic,meson6-timer";
> +		reg = <0xc1109940 0x14>;
> +		interrupts = <0 10 1>;
> +	};
> +
> +	soc@c8100000 {

What's the unit-address for? This node doesn't have a reg or compatible.

> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		uart_AO: serial@c81004c0 {
> +			compatible = "amlogic,meson-uart";
> +			reg = <0xc81004c0 0x14>;
> +			interrupts = <0 90 1>;
> +			clocks = <&clk81>;
> +			status = "disabled";
> +		};
> +
> +		uart_A: serial@c81084c0 {
> +			compatible = "amlogic,meson-uart";
> +			reg = <0xc81084c0 0x14>;
> +			interrupts = <0 90 1>;
> +			clocks = <&clk81>;
> +			status = "disabled";
> +		};
> +
> +		uart_B: serial@c81084dc {
> +			compatible = "amlogic,meson-uart";
> +			reg = <0xc81084dc 0x14>;
> +			interrupts = <0 90 1>;
> +			clocks = <&clk81>;
> +			status = "disabled";
> +		};
> +
> +		uart_C: serial@c8108700 {
> +			compatible = "amlogic,meson-uart";
> +			reg = <0xc8108700 0x14>;
> +			interrupts = <0 90 1>;
> +			clocks = <&clk81>;
> +			status = "disabled";

I guess these are disabled because they aren't always wired up?

> +		};
> +	};
> +}; /* end of / */
> +
> diff --git a/arch/arm/boot/dts/meson6-atv1200.dts b/arch/arm/boot/dts/meson6-atv1200.dts
> new file mode 100644
> index 0000000..b358402
> --- /dev/null
> +++ b/arch/arm/boot/dts/meson6-atv1200.dts
> @@ -0,0 +1,27 @@
> +/*
> + * Copyright 2014 Carlo Caione <carlo@caione.org>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +
> +/dts-v1/;
> +/include/ "meson6.dtsi"
> +
> +/ {
> +	model = "Geniatech ATV1200";
> +	compatible = "geniatech,atv1200";
> +
> +	memory {
> +		reg = <0x40000000 0x80000000>;
> +	};
> +
> +	soc@c8100000 {
> +		uart_AO: serial@c81004c0 {
> +			status = "okay";
> +		};
> +	};
> +}; /* end of / */
> +
> diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi
> new file mode 100644
> index 0000000..d62add4
> --- /dev/null
> +++ b/arch/arm/boot/dts/meson6.dtsi
> @@ -0,0 +1,44 @@
> +/*
> + * Copyright 2014 Carlo Caione <carlo@caione.org>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +
> +/include/ "meson.dtsi"
> +
> +/ {
> +	model = "Amlogic Meson6 SoC";
> +	compatible = "amlogic,meson6", "amlogic,8726_mx";
> +
> +	interrupt-parent = <&gic>;
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a9";
> +			reg = <0x200>;
> +		};
> +
> +		cpu@1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a9";
> +			reg = <0x1>;
> +		};
> +	};
> +
> +	clocks {
> +		#address-cells = <1>;
> +
> +		clk81: clk@0 {
> +			#clock-cells = <0>;
> +			compatible = "fixed-clock";
> +			clock-frequency = <200000000>;
> +		};
> +	};

There is really no need to put clocks in a container.

Just put them under the root, and drop the unit-address.

Thanks,
Mark.

Re: [PATCH 5/7] ARM: meson: dts: add basic Meson/Meson6/Meson6-atv1200 DTSI/DTS

[Carlo Caione]

On Mon, Aug 18, 2014 at 05:17:44PM +0100, Mark Rutland wrote:
> On Sun, Aug 17, 2014 at 11:49:52AM +0100, Carlo Caione wrote:

<cut>

> > +	soc@c8100000 {
> 
> What's the unit-address for? This node doesn't have a reg or compatible.

I used it to indicate the starting address of the memory mapped region.

> > +		compatible = "simple-bus";
> > +		#address-cells = <1>;
> > +		#size-cells = <1>;
> > +		ranges;
> > +
> > +		uart_AO: serial@c81004c0 {
> > +			compatible = "amlogic,meson-uart";
> > +			reg = <0xc81004c0 0x14>;
> > +			interrupts = <0 90 1>;
> > +			clocks = <&clk81>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart_A: serial@c81084c0 {
> > +			compatible = "amlogic,meson-uart";
> > +			reg = <0xc81084c0 0x14>;
> > +			interrupts = <0 90 1>;
> > +			clocks = <&clk81>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart_B: serial@c81084dc {
> > +			compatible = "amlogic,meson-uart";
> > +			reg = <0xc81084dc 0x14>;
> > +			interrupts = <0 90 1>;
> > +			clocks = <&clk81>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart_C: serial@c8108700 {
> > +			compatible = "amlogic,meson-uart";
> > +			reg = <0xc8108700 0x14>;
> > +			interrupts = <0 90 1>;
> > +			clocks = <&clk81>;
> > +			status = "disabled";
> 
> I guess these are disabled because they aren't always wired up?

Yes

<cut>

> > +	clocks {
> > +		#address-cells = <1>;
> > +
> > +		clk81: clk@0 {
> > +			#clock-cells = <0>;
> > +			compatible = "fixed-clock";
> > +			clock-frequency = <200000000>;
> > +		};
> > +	};
> 
> There is really no need to put clocks in a container.
> 
> Just put them under the root, and drop the unit-address.

I'll do, thanks.

-- 
Carlo Caione

Re: [PATCH 5/7] ARM: meson: dts: add basic Meson/Meson6/Meson6-atv1200 DTSI/DTS

[Andreas Färber]

Hi,

Am 17.08.2014 12:49, schrieb Carlo Caione:
> The Meson6 SoC is produced by Amlogic inc. and it is based on 2 Cortex A9
> and an ARM Mali-400 GPU.
> This patch adds two basic DTSI for the preliminary support of Meson and
> Meson6 SoCs. Another DTS is also added for supporting the atv1200 board,
> produced by Geniatech inc.
> 
> Signed-off-by: Carlo Caione <carlo@caione.org>
> ---
>  arch/arm/boot/dts/Makefile           |  1 +
>  arch/arm/boot/dts/meson.dtsi         | 75 ++++++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/meson6-atv1200.dts | 27 +++++++++++++
>  arch/arm/boot/dts/meson6.dtsi        | 44 +++++++++++++++++++++
>  4 files changed, 147 insertions(+)
>  create mode 100644 arch/arm/boot/dts/meson.dtsi
>  create mode 100644 arch/arm/boot/dts/meson6-atv1200.dts
>  create mode 100644 arch/arm/boot/dts/meson6.dtsi
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index b8c5cd3..604acce 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -159,6 +159,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \
>  	kirkwood-ts419-6282.dtb
>  dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
>  dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
> +dtb-$(CONFIG_MACH_MESON6) += meson6-atv1200.dtb
>  dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb
>  dtb-$(CONFIG_ARCH_MXC) += \
>  	imx25-eukrea-mbimxsd25-baseboard.dtb \
> diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
> new file mode 100644
> index 0000000..934bb2c
> --- /dev/null
> +++ b/arch/arm/boot/dts/meson.dtsi
> @@ -0,0 +1,75 @@
> +/*
> + * Copyright 2014 Carlo Caione <carlo@caione.org>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +
> +/include/ "skeleton.dtsi"
> +
> +/ {
> +	interrupt-parent = <&gic>;
> +
> +	aliases {
> +		serial0 = &uart_AO;
> +		serial1 = &uart_A;
> +		serial2 = &uart_B;
> +		serial3 = &uart_C;
> +	};
> +
> +	gic: interrupt-controller@c4301000 {
> +		compatible = "arm,cortex-a9-gic";
> +		reg = <0xc4301000 0x1000>,
> +		      <0xc4300100 0x0100>;
> +		interrupt-controller;
> +		#interrupt-cells = <3>;
> +	};
> +
> +	timer@c1109940 {
> +		compatible = "amlogic,meson6-timer";
> +		reg = <0xc1109940 0x14>;
> +		interrupts = <0 10 1>;
> +	};
> +
> +	soc@c8100000 {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		uart_AO: serial@c81004c0 {
> +			compatible = "amlogic,meson-uart";
> +			reg = <0xc81004c0 0x14>;
> +			interrupts = <0 90 1>;
> +			clocks = <&clk81>;
> +			status = "disabled";
> +		};
> +
> +		uart_A: serial@c81084c0 {
> +			compatible = "amlogic,meson-uart";
> +			reg = <0xc81084c0 0x14>;
> +			interrupts = <0 90 1>;
> +			clocks = <&clk81>;
> +			status = "disabled";
> +		};
> +
> +		uart_B: serial@c81084dc {
> +			compatible = "amlogic,meson-uart";
> +			reg = <0xc81084dc 0x14>;
> +			interrupts = <0 90 1>;
> +			clocks = <&clk81>;
> +			status = "disabled";
> +		};
> +
> +		uart_C: serial@c8108700 {
> +			compatible = "amlogic,meson-uart";
> +			reg = <0xc8108700 0x14>;
> +			interrupts = <0 90 1>;
> +			clocks = <&clk81>;
> +			status = "disabled";
> +		};
> +	};
> +}; /* end of / */
> +

Trailing blank line.

> diff --git a/arch/arm/boot/dts/meson6-atv1200.dts b/arch/arm/boot/dts/meson6-atv1200.dts
> new file mode 100644
> index 0000000..b358402
> --- /dev/null
> +++ b/arch/arm/boot/dts/meson6-atv1200.dts
> @@ -0,0 +1,27 @@
> +/*
> + * Copyright 2014 Carlo Caione <carlo@caione.org>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +
> +/dts-v1/;
> +/include/ "meson6.dtsi"
> +
> +/ {
> +	model = "Geniatech ATV1200";
> +	compatible = "geniatech,atv1200";
> +
> +	memory {
> +		reg = <0x40000000 0x80000000>;
> +	};
> +
> +	soc@c8100000 {
> +		uart_AO: serial@c81004c0 {
> +			status = "okay";
> +		};
> +	};
> +}; /* end of / */
> +

Since this is a new SoC, just override the status down here:

&uart_A0 {
	status = "okay";
};

That decouples it from how you name the SoC node exactly.

> diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi
> new file mode 100644
> index 0000000..d62add4
> --- /dev/null
> +++ b/arch/arm/boot/dts/meson6.dtsi
> @@ -0,0 +1,44 @@
> +/*
> + * Copyright 2014 Carlo Caione <carlo@caione.org>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +
> +/include/ "meson.dtsi"
> +
> +/ {
> +	model = "Amlogic Meson6 SoC";
> +	compatible = "amlogic,meson6", "amlogic,8726_mx";

In the cover letter you said AML8726-MX - why underscore here?

In 3.17-rc1 at least I don't see the amlogic prefix documented. If so,
you should probably add it to
Documentation/devicetree/bindings/vendor-prefixes.txt. Similarly, should
you document some of those amlogic,* compatible strings in a new
.../bindings/arm/amlogic.txt file?

Same applies to geniatech further above. checkpatch.pl should warn about
undocumented compatible strings.

Cf.
http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/submitting-patches.txt

> +
> +	interrupt-parent = <&gic>;
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a9";
> +			reg = <0x200>;
> +		};
> +
> +		cpu@1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a9";
> +			reg = <0x1>;
> +		};
> +	};
> +
> +	clocks {
> +		#address-cells = <1>;
> +
> +		clk81: clk@0 {
> +			#clock-cells = <0>;
> +			compatible = "fixed-clock";
> +			clock-frequency = <200000000>;
> +		};
> +	};
> +}; /* end of / */

Cheers,
Andreas

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[PATCH 6/7] ARM: meson: update defconfigs

[Carlo Caione]

This patch updates the multi_v7_defconfig with the CONFIG_* needed by
the just added Meson anch. It also adds a new defconfig specifically for
the Meson SoCs.

Signed-off-by: Carlo Caione <carlo@caione.org>
---
 arch/arm/configs/meson_defconfig    | 99 +++++++++++++++++++++++++++++++++++++
 arch/arm/configs/multi_v7_defconfig |  3 ++
 2 files changed, 102 insertions(+)
 create mode 100644 arch/arm/configs/meson_defconfig

diff --git a/arch/arm/configs/meson_defconfig b/arch/arm/configs/meson_defconfig
new file mode 100644
index 0000000..3c9d976
--- /dev/null
+++ b/arch/arm/configs/meson_defconfig
@@ -0,0 +1,99 @@
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_PERF_EVENTS=y
+CONFIG_ARCH_MESON=y
+CONFIG_SMP=y
+CONFIG_HAVE_ARM_ARCH_TIMER=y
+CONFIG_ARM_PSCI=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_ATA=y
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+CONFIG_STMMAC_ETH=y
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_SERIAL_MESON=y
+CONFIG_SERIAL_MESON_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_SPI=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_RESET=y
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_MFD_AXP20X=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_MMC=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_INTF_SYSFS is not set
+# CONFIG_RTC_INTF_PROC is not set
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_GENERIC_PHY=y
+CONFIG_EXT4_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_FS=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 5fb95fb..5b44796 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -29,6 +29,7 @@ CONFIG_ARCH_HISI=y
 CONFIG_ARCH_HI3xxx=y
 CONFIG_ARCH_HIX5HD2=y
 CONFIG_ARCH_KEYSTONE=y
+CONFIG_ARCH_MESON=y
 CONFIG_ARCH_MXC=y
 CONFIG_SOC_IMX51=y
 CONFIG_SOC_IMX53=y
@@ -173,6 +174,8 @@ CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_DW=y
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_MESON=y
+CONFIG_SERIAL_MESON_CONSOLE=y
 CONFIG_SERIAL_SAMSUNG=y
 CONFIG_SERIAL_SAMSUNG_CONSOLE=y
 CONFIG_SERIAL_SIRFSOC=y
-- 
1.9.1

Re: [PATCH 6/7] ARM: meson: update defconfigs

[Matthias Brugger]

On 17/08/14 12:49, Carlo Caione wrote:
> This patch updates the multi_v7_defconfig with the CONFIG_* needed by
> the just added Meson anch. It also adds a new defconfig specifically for
> the Meson SoCs.
>
> Signed-off-by: Carlo Caione <carlo@caione.org>
> ---
>   arch/arm/configs/meson_defconfig    | 99 +++++++++++++++++++++++++++++++++++++
>   arch/arm/configs/multi_v7_defconfig |  3 ++
>   2 files changed, 102 insertions(+)
>   create mode 100644 arch/arm/configs/meson_defconfig
>
> diff --git a/arch/arm/configs/meson_defconfig b/arch/arm/configs/meson_defconfig
> new file mode 100644
> index 0000000..3c9d976
> --- /dev/null
> +++ b/arch/arm/configs/meson_defconfig

I doubt that we need a meson_defconfig when we can get the SoC up and 
running using multi_v7_defconfig.

> @@ -0,0 +1,99 @@
> +CONFIG_NO_HZ=y
> +CONFIG_HIGH_RES_TIMERS=y
> +CONFIG_BLK_DEV_INITRD=y
> +CONFIG_PERF_EVENTS=y
> +CONFIG_ARCH_MESON=y
> +CONFIG_SMP=y
> +CONFIG_HAVE_ARM_ARCH_TIMER=y
> +CONFIG_ARM_PSCI=y
> +CONFIG_AEABI=y
> +CONFIG_HIGHMEM=y
> +CONFIG_HIGHPTE=y
> +CONFIG_ARM_APPENDED_DTB=y
> +CONFIG_ARM_ATAG_DTB_COMPAT=y
> +CONFIG_VFP=y
> +CONFIG_NEON=y
> +CONFIG_PM_RUNTIME=y
> +CONFIG_NET=y
> +CONFIG_PACKET=y
> +CONFIG_UNIX=y
> +CONFIG_INET=y
> +CONFIG_IP_PNP=y
> +CONFIG_IP_PNP_DHCP=y
> +CONFIG_IP_PNP_BOOTP=y
> +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
> +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
> +# CONFIG_INET_XFRM_MODE_BEET is not set
> +# CONFIG_INET_LRO is not set
> +# CONFIG_INET_DIAG is not set
> +# CONFIG_IPV6 is not set
> +# CONFIG_WIRELESS is not set
> +CONFIG_DEVTMPFS=y
> +CONFIG_DEVTMPFS_MOUNT=y
> +CONFIG_BLK_DEV_SD=y
> +CONFIG_ATA=y
> +CONFIG_NETDEVICES=y
> +# CONFIG_NET_VENDOR_ARC is not set
> +# CONFIG_NET_CADENCE is not set
> +# CONFIG_NET_VENDOR_BROADCOM is not set
> +# CONFIG_NET_VENDOR_CIRRUS is not set
> +# CONFIG_NET_VENDOR_FARADAY is not set
> +# CONFIG_NET_VENDOR_INTEL is not set
> +# CONFIG_NET_VENDOR_MARVELL is not set
> +# CONFIG_NET_VENDOR_MICREL is not set
> +# CONFIG_NET_VENDOR_MICROCHIP is not set
> +# CONFIG_NET_VENDOR_NATSEMI is not set
> +# CONFIG_NET_VENDOR_SAMSUNG is not set
> +# CONFIG_NET_VENDOR_SEEQ is not set
> +# CONFIG_NET_VENDOR_SMSC is not set
> +CONFIG_STMMAC_ETH=y
> +# CONFIG_NET_VENDOR_VIA is not set
> +# CONFIG_NET_VENDOR_WIZNET is not set
> +# CONFIG_WLAN is not set
> +# CONFIG_INPUT_MOUSEDEV is not set
> +# CONFIG_INPUT_KEYBOARD is not set
> +# CONFIG_INPUT_MOUSE is not set
> +CONFIG_SERIAL_MESON=y
> +CONFIG_SERIAL_MESON_CONSOLE=y
> +# CONFIG_HW_RANDOM is not set
> +CONFIG_I2C=y
> +CONFIG_I2C_CHARDEV=y
> +CONFIG_SPI=y
> +CONFIG_GPIOLIB=y
> +CONFIG_GPIO_SYSFS=y
> +CONFIG_POWER_SUPPLY=y
> +CONFIG_POWER_RESET=y
> +# CONFIG_HWMON is not set
> +CONFIG_WATCHDOG=y
> +CONFIG_WATCHDOG_CORE=y
> +CONFIG_MFD_AXP20X=y
> +CONFIG_REGULATOR=y
> +CONFIG_REGULATOR_FIXED_VOLTAGE=y
> +CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
> +CONFIG_REGULATOR_GPIO=y
> +CONFIG_USB=y
> +CONFIG_USB_EHCI_HCD=y
> +CONFIG_USB_EHCI_HCD_PLATFORM=y
> +CONFIG_USB_OHCI_HCD=y
> +CONFIG_USB_OHCI_HCD_PLATFORM=y
> +CONFIG_MMC=y
> +CONFIG_NEW_LEDS=y
> +CONFIG_LEDS_CLASS=y
> +CONFIG_LEDS_GPIO=y
> +CONFIG_LEDS_TRIGGERS=y
> +CONFIG_LEDS_TRIGGER_HEARTBEAT=y
> +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
> +CONFIG_RTC_CLASS=y
> +# CONFIG_RTC_INTF_SYSFS is not set
> +# CONFIG_RTC_INTF_PROC is not set
> +# CONFIG_IOMMU_SUPPORT is not set
> +CONFIG_GENERIC_PHY=y
> +CONFIG_EXT4_FS=y
> +CONFIG_VFAT_FS=y
> +CONFIG_TMPFS=y
> +CONFIG_NFS_FS=y
> +CONFIG_NFS_V3_ACL=y
> +CONFIG_NFS_V4=y
> +CONFIG_ROOT_NFS=y
> +CONFIG_PRINTK_TIME=y
> +CONFIG_DEBUG_FS=y
> diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
> index 5fb95fb..5b44796 100644
> --- a/arch/arm/configs/multi_v7_defconfig
> +++ b/arch/arm/configs/multi_v7_defconfig
> @@ -29,6 +29,7 @@ CONFIG_ARCH_HISI=y
>   CONFIG_ARCH_HI3xxx=y
>   CONFIG_ARCH_HIX5HD2=y
>   CONFIG_ARCH_KEYSTONE=y
> +CONFIG_ARCH_MESON=y
>   CONFIG_ARCH_MXC=y
>   CONFIG_SOC_IMX51=y
>   CONFIG_SOC_IMX53=y
> @@ -173,6 +174,8 @@ CONFIG_SERIAL_8250_CONSOLE=y
>   CONFIG_SERIAL_8250_DW=y
>   CONFIG_SERIAL_AMBA_PL011=y
>   CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
> +CONFIG_SERIAL_MESON=y
> +CONFIG_SERIAL_MESON_CONSOLE=y
>   CONFIG_SERIAL_SAMSUNG=y
>   CONFIG_SERIAL_SAMSUNG_CONSOLE=y
>   CONFIG_SERIAL_SIRFSOC=y
>

Re: [PATCH 6/7] ARM: meson: update defconfigs

[Carlo Caione]

On Mon, Aug 18, 2014 at 12:31:22PM +0200, Matthias Brugger wrote:
> 
> 
> On 17/08/14 12:49, Carlo Caione wrote:
> >This patch updates the multi_v7_defconfig with the CONFIG_* needed by
> >the just added Meson anch. It also adds a new defconfig specifically for
> >the Meson SoCs.
> >
> >Signed-off-by: Carlo Caione <carlo@caione.org>
> >---
> >  arch/arm/configs/meson_defconfig    | 99 +++++++++++++++++++++++++++++++++++++
> >  arch/arm/configs/multi_v7_defconfig |  3 ++
> >  2 files changed, 102 insertions(+)
> >  create mode 100644 arch/arm/configs/meson_defconfig
> >
> >diff --git a/arch/arm/configs/meson_defconfig b/arch/arm/configs/meson_defconfig
> >new file mode 100644
> >index 0000000..3c9d976
> >--- /dev/null
> >+++ b/arch/arm/configs/meson_defconfig
> 
> I doubt that we need a meson_defconfig when we can get the SoC up
> and running using multi_v7_defconfig.

It was because multi_v7_defconfig is becoming a bit too crowded. But
I'll get rid of it in v2.

Thank you,

-- 
Carlo Caione

[PATCH 7/7] ARM: meson: update documentation (uart, timer and vendors)

[Carlo Caione]

New UART and timer bindings are documented. A new vendor is added to the
vendors list.

Signed-off-by: Carlo Caione <carlo-KA+7E9HrN00dnm+yROfE0A@public.gmane.org>
---
 .../devicetree/bindings/serial/amlogic,meson-uart.txt   | 17 +++++++++++++++++
 .../devicetree/bindings/timer/amlogic,meson6-timer.txt  | 16 ++++++++++++++++
 Documentation/devicetree/bindings/vendor-prefixes.txt   |  1 +
 3 files changed, 34 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt
 create mode 100644 Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt

diff --git a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt
new file mode 100644
index 0000000..fa1935a
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt
@@ -0,0 +1,17 @@
+Amlogic Meson UART
+
+Required properties:
+- compatible : Should be "amlogic,meson-uart"
+- reg : Address and length of the register set
+- interrupts : Should contain uart interrupt
+- clocks: phandle to the source clock
+
+Example:
+
+uart0: serial@c81004c0 {
+	compatible = "amlogic,meson-uart";
+	reg = <0xc81004c0 0x14>;
+	interrupts = <0 90 1>;
+	clocks = <&clk81>;
+};
+
diff --git a/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt b/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt
new file mode 100644
index 0000000..cf89894
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt
@@ -0,0 +1,16 @@
+Amlogic Meson6 SoCs Timer Controller
+
+Required properties:
+
+- compatible : should be "amlogic,meson6-timer.txt"
+- reg : Specifies base physical address and size of the registers.
+- interrupts : The interrupt of the first timer
+
+Example:
+
+timer@c1109940 {
+	compatible = "amlogic,meson6-timer";
+	reg = <0xc1109940 0x14>;
+	interrupts = <0 10 1>;
+};
+
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index ac7269f..5cf0618 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -14,6 +14,7 @@ allwinner	Allwinner Technology Co., Ltd.
 altr	Altera Corp.
 amcc	Applied Micro Circuits Corporation (APM, formally AMCC)
 amd	Advanced Micro Devices (AMD), Inc.
+amlogic	Amlogic, Inc.
 ams	AMS AG
 amstaos	AMS-Taos Inc.
 apm	Applied Micro Circuits Corporation (APM)
-- 
1.9.1

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Re: [PATCH 7/7] ARM: meson: update documentation (uart, timer and vendors)

[Matthias Brugger]

On 17/08/14 12:49, Carlo Caione wrote:
> New UART and timer bindings are documented. A new vendor is added to the
> vendors list.
>
> Signed-off-by: Carlo Caione <carlo@caione.org>
> ---
>   .../devicetree/bindings/serial/amlogic,meson-uart.txt   | 17 +++++++++++++++++
>   .../devicetree/bindings/timer/amlogic,meson6-timer.txt  | 16 ++++++++++++++++
>   Documentation/devicetree/bindings/vendor-prefixes.txt   |  1 +
>   3 files changed, 34 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt
>   create mode 100644 Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt

This should be three patches for the different files. It might happen, 
that for example your timer driver get merged through a different tree 
then arm-soc. For the merge, the driver and the documentation should go 
togehter.

>
> diff --git a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt
> new file mode 100644
> index 0000000..fa1935a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt
> @@ -0,0 +1,17 @@
> +Amlogic Meson UART
> +
> +Required properties:
> +- compatible : Should be "amlogic,meson-uart"
> +- reg : Address and length of the register set
> +- interrupts : Should contain uart interrupt
> +- clocks: phandle to the source clock
> +
> +Example:
> +
> +uart0: serial@c81004c0 {
> +	compatible = "amlogic,meson-uart";
> +	reg = <0xc81004c0 0x14>;
> +	interrupts = <0 90 1>;
> +	clocks = <&clk81>;
> +};
> +
> diff --git a/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt b/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt
> new file mode 100644
> index 0000000..cf89894
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt
> @@ -0,0 +1,16 @@
> +Amlogic Meson6 SoCs Timer Controller
> +
> +Required properties:
> +
> +- compatible : should be "amlogic,meson6-timer.txt"
> +- reg : Specifies base physical address and size of the registers.
> +- interrupts : The interrupt of the first timer
> +
> +Example:
> +
> +timer@c1109940 {
> +	compatible = "amlogic,meson6-timer";
> +	reg = <0xc1109940 0x14>;
> +	interrupts = <0 10 1>;
> +};
> +
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
> index ac7269f..5cf0618 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
> @@ -14,6 +14,7 @@ allwinner	Allwinner Technology Co., Ltd.
>   altr	Altera Corp.
>   amcc	Applied Micro Circuits Corporation (APM, formally AMCC)
>   amd	Advanced Micro Devices (AMD), Inc.
> +amlogic	Amlogic, Inc.
>   ams	AMS AG
>   amstaos	AMS-Taos Inc.
>   apm	Applied Micro Circuits Corporation (APM)
>

Re: [PATCH 7/7] ARM: meson: update documentation (uart, timer and vendors)

[Carlo Caione]

On Mon, Aug 18, 2014 at 12:36:47PM +0200, Matthias Brugger wrote:
> 
> 
> On 17/08/14 12:49, Carlo Caione wrote:
> >New UART and timer bindings are documented. A new vendor is added to the
> >vendors list.
> >
> >Signed-off-by: Carlo Caione <carlo@caione.org>
> >---
> >  .../devicetree/bindings/serial/amlogic,meson-uart.txt   | 17 +++++++++++++++++
> >  .../devicetree/bindings/timer/amlogic,meson6-timer.txt  | 16 ++++++++++++++++
> >  Documentation/devicetree/bindings/vendor-prefixes.txt   |  1 +
> >  3 files changed, 34 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt
> >  create mode 100644 Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt
> 
> This should be three patches for the different files. It might
> happen, that for example your timer driver get merged through a
> different tree then arm-soc. For the merge, the driver and the
> documentation should go togehter.

Right. Thank you for pointing this out.

Best,

-- 
Carlo Caione

Re: [PATCH 7/7] ARM: meson: update documentation (uart, timer and vendors)

[Andreas Färber]

Am 17.08.2014 12:49, schrieb Carlo Caione:
> New UART and timer bindings are documented. A new vendor is added to the
> vendors list.
> 
> Signed-off-by: Carlo Caione <carlo@caione.org>
> ---
>  .../devicetree/bindings/serial/amlogic,meson-uart.txt   | 17 +++++++++++++++++
>  .../devicetree/bindings/timer/amlogic,meson6-timer.txt  | 16 ++++++++++++++++
>  Documentation/devicetree/bindings/vendor-prefixes.txt   |  1 +
>  3 files changed, 34 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt
>  create mode 100644 Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt
[...]
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
> index ac7269f..5cf0618 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
> @@ -14,6 +14,7 @@ allwinner	Allwinner Technology Co., Ltd.
>  altr	Altera Corp.
>  amcc	Applied Micro Circuits Corporation (APM, formally AMCC)
>  amd	Advanced Micro Devices (AMD), Inc.
> +amlogic	Amlogic, Inc.
>  ams	AMS AG
>  amstaos	AMS-Taos Inc.
>  apm	Applied Micro Circuits Corporation (APM)

Sorry, here's the vendor prefix I was asking about. Please split it off
into its own patch and best order it before the first use.

Documentation of SoC and board seem to be indeed missing though.

Cheers,
Andreas

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Re: [PATCH 0/7] ARM: meson: add preliminary support for MesonX/Meson6 SoCs

[Beniamino Galvani]

On Sun, Aug 17, 2014 at 12:49:47PM +0200, Carlo Caione wrote:
> Amlogic AML8726-MX (codename Meson6) is a highly integrated multimedia
> application processor SoC for Multimedia Internet Device (MID), tablet
> and Set Top Box (STB). It integrates a powerful CPU, a 2D/3D graphics
> subsystem and a state-of-the-art video decoding engine together with
> all major peripherals. It is manufactured by Amlogic, inc.
> 
> This patchset introduces preliminary support for Meson6-based SoCs but
> several IPs and drivers are common among all the MesonX SoCs.

Hi Carlo,

nice job! The patches work fine on a Tronsmart Vega S89 Elite TV box
(Meson8 S802 SoC) just changing the fixed-clock frequency in the dts.

Beniamino

> 
> Amlogic doesn't release any documentation about their SoCs, so the code
> has been reverse-engineered from the messy source code released at:
> 
> http://openlinux.amlogic.com:8000/download/
> 
> Carlo Caione (7):
>   ARM: meson: debug: add debug UART for earlyprintk support
>   ARM: meson: serial: add MesonX SoC on-chip uart driver
>   ARM: meson6: clocksource: add Meson6 timer support
>   ARM: meson: add basic support for MesonX SoCs
>   ARM: meson: dts: add basic Meson/Meson6/Meson6-atv1200 DTSI/DTS
>   ARM: meson: update defconfigs
>   ARM: meson: update documentation (uart, timer and vendors)
> 
>  .../bindings/serial/amlogic,meson-uart.txt         |  17 +
>  .../bindings/timer/amlogic,meson6-timer.txt        |  16 +
>  .../devicetree/bindings/vendor-prefixes.txt        |   1 +
>  arch/arm/Kconfig                                   |   2 +
>  arch/arm/Kconfig.debug                             |  14 +-
>  arch/arm/Makefile                                  |   1 +
>  arch/arm/boot/dts/Makefile                         |   1 +
>  arch/arm/boot/dts/meson.dtsi                       |  75 +++
>  arch/arm/boot/dts/meson6-atv1200.dts               |  27 +
>  arch/arm/boot/dts/meson6.dtsi                      |  44 ++
>  arch/arm/configs/meson_defconfig                   |  99 ++++
>  arch/arm/configs/multi_v7_defconfig                |   3 +
>  arch/arm/include/debug/meson.S                     |  35 ++
>  arch/arm/mach-meson/Kconfig                        |  13 +
>  arch/arm/mach-meson/Makefile                       |   1 +
>  arch/arm/mach-meson/meson.c                        |  36 ++
>  drivers/clocksource/Kconfig                        |   3 +
>  drivers/clocksource/Makefile                       |   1 +
>  drivers/clocksource/meson6_timer.c                 | 187 ++++++
>  drivers/tty/serial/Kconfig                         |  18 +
>  drivers/tty/serial/Makefile                        |   1 +
>  drivers/tty/serial/meson_uart.c                    | 634 +++++++++++++++++++++
>  include/uapi/linux/serial_core.h                   |   3 +
>  23 files changed, 1230 insertions(+), 2 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt
>  create mode 100644 Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt
>  create mode 100644 arch/arm/boot/dts/meson.dtsi
>  create mode 100644 arch/arm/boot/dts/meson6-atv1200.dts
>  create mode 100644 arch/arm/boot/dts/meson6.dtsi
>  create mode 100644 arch/arm/configs/meson_defconfig
>  create mode 100644 arch/arm/include/debug/meson.S
>  create mode 100644 arch/arm/mach-meson/Kconfig
>  create mode 100644 arch/arm/mach-meson/Makefile
>  create mode 100644 arch/arm/mach-meson/meson.c
>  create mode 100644 drivers/clocksource/meson6_timer.c
>  create mode 100644 drivers/tty/serial/meson_uart.c
> 
> -- 
> 1.9.1
> 

Re: [PATCH 0/7] ARM: meson: add preliminary support for MesonX/Meson6 SoCs

[Carlo Caione]

On Sun, Aug 17, 2014 at 4:29 PM, Beniamino Galvani <b.galvani@gmail.com> wrote:

> nice job! The patches work fine on a Tronsmart Vega S89 Elite TV box
> (Meson8 S802 SoC) just changing the fixed-clock frequency in the dts.

This means that probably also the timer driver can be somehow shared
between Meson6 and Meson8. If this is confirmed in v2 I can make a
generic clocksource/clockevents driver for both the architectures.

Thanks,

-- 
Carlo Caione