From: Tony Lindgren <tony@atomide.com>
To: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Rob Herring <robh+dt@kernel.org>, Nishanth Menon <nm@ti.com>,
Santosh Shilimkar <ssantosh@kernel.org>,
Will Deacon <will.deacon@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Mark Rutland <mark.rutland@arm.com>,
"open list:SERIAL DRIVERS" <linux-serial@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
devicetree@vger.kernel.org,
"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
<linux-arm-kernel@lists.infradead.org>,
Vignesh R <vigneshr@ti.com>, Tero Kristo <t-kristo@ti.com>,
Russell King <linux@armlinux.org.uk>,
Sudeep Holla <sudeep.holla@arm.com>
Subject: Re: Re: [RFC PATCH 5/6] arm64: dts: ti: Add Support for AM654 SoC
Date: Mon, 20 Aug 2018 07:31:53 -0700 [thread overview]
Message-ID: <20180820143153.GD7523@atomide.com> (raw)
In-Reply-To: <454c277e-8a63-81cb-b341-a50f4e25cbea@ti.com>
* Kishon Vijay Abraham I <kishon@ti.com> [180808 06:35]:
> On Tuesday 05 June 2018 07:35 PM, Rob Herring wrote:
> > Really need 64-bit addresses and sizes? Use ranges to limit the
> > address space if possible.
>
> We now have address-cells as <1>,
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/ti/k3-am65.dtsi#n49
>
> However each PCIe instance has 2 data regions and one of the regions
> (PCIE0_CORE_CORE_DAT_SLV_PCIE_DAT1/PCIE1_CORE_CORE_DAT_SLV_PCIE_DAT1 specified
> in the "MAIN Domain Memory Map" table of TRM http://www.ti.com/lit/pdf/spruid7)
> is above the 32bit region and requires 2 cells to specify the start address.
> This region is used to access MEM_SPACE of PCIe endpoint when operating in root
> complex mode and access memory of PCI root complex when operating in endpoint mode.
>
> In order to describe this, should we change the address-cells back to <2> or do
> you suggest any other alternatives?
It's probably best to have the top level cbass interconnect use
#size-cells = <2> and then have it's child interconnects have
#size-cells = <1> if they don't need ranges above 4GB.
BTW, what's the difference between all these three similar PCIE
ranges?
PCIE0_CORE_CORE_DAT_SLV_PCIE_CORE 0x0005500000 0x0005600000 1 MB
PCIE1_CORE_CORE_DAT_SLV_PCIE_CORE 0x0005600000 0x0005700000 1 MB
PCIE0_CORE_CORE_DAT_SLV_PCIE_DAT0 0x0010000000 0x0018000000 128 MB
PCIE1_CORE_CORE_DAT_SLV_PCIE_DAT0 0x0018000000 0x0020000000 128 MB
PCIE0_CORE_CORE_DAT_SLV_PCIE_DAT1 0x4000000000 0x4100000000 4 GB
PCIE1_CORE_CORE_DAT_SLV_PCIE_DAT1 0x4100000000 0x4200000000 4 GB
Regards,
Tony
next prev parent reply other threads:[~2018-08-20 14:31 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <=<20180605060125.9518-1-nm@ti.com>
2018-06-05 6:05 ` [RFC PATCH 5/6] arm64: dts: ti: Add Support for AM654 SoC Nishanth Menon
2018-06-05 6:05 ` [RFC PATCH 6/6] arm64: dts: ti: Add support for AM654 EVM base board Nishanth Menon
2018-06-05 14:05 ` [RFC PATCH 5/6] arm64: dts: ti: Add Support for AM654 SoC Rob Herring
2018-06-05 14:14 ` Tony Lindgren
2018-06-07 23:38 ` Nishanth Menon
2018-06-14 12:38 ` Tony Lindgren
2018-06-14 13:04 ` Nishanth Menon
2018-06-15 5:01 ` Tony Lindgren
2018-06-15 13:38 ` Sekhar Nori
2018-08-20 14:21 ` Tony Lindgren
2018-08-08 6:31 ` Kishon Vijay Abraham I
2018-08-20 14:31 ` Tony Lindgren [this message]
2018-08-27 3:02 ` Kishon Vijay Abraham I
2018-08-27 15:55 ` Tony Lindgren
2018-08-28 1:22 ` Nishanth Menon
2018-08-28 3:39 ` Kishon Vijay Abraham I
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