From: Thierry Reding <thierry.reding@gmail.com>
To: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Cc: gregkh@linuxfoundation.org, robh+dt@kernel.org,
mark.rutland@arm.com, jonathanh@nvidia.com, ldewangan@nvidia.com,
jslaby@suse.com, linux-serial@vger.kernel.org,
devicetree@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org, Ahung Cheng <ahcheng@nvidia.com>,
Shardar Mohammed <smohammed@nvidia.com>
Subject: Re: [PATCH 03/14] serial: tegra: avoid reg access when clk disabled
Date: Tue, 13 Aug 2019 11:45:56 +0200 [thread overview]
Message-ID: <20190813094556.GH1137@ulmo> (raw)
In-Reply-To: <1565609303-27000-4-git-send-email-kyarlagadda@nvidia.com>
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On Mon, Aug 12, 2019 at 04:58:12PM +0530, Krishna Yarlagadda wrote:
> From: Ahung Cheng <ahcheng@nvidia.com>
>
> This avoids two race conditions from the UART shutdown sequence both
> leading to 'Machine check error in AXI2APB' and kernel oops.
>
> One was that the clock was disabled before the DMA was terminated making
> it possible for the DMA callbacks to be called after the clock was
> disabled. These callbacks could write to the UART registers causing
> timeout.
>
> The second was that the clock was disabled before the UART was
> completely flagged as closed. This is done after the shutdown is called
> and a new write could be started after the clock was disabled.
> tegra_uart_start_pio_tx could be called causing timeout.
>
> Given that the baud rate is reset at the end of shutdown sequence, this
> fix is to examine the baud rate to avoid register access from both race
> conditions.
>
> Besides, terminate the DMA before disabling the clock.
>
> Signed-off-by: Ahung Cheng <ahcheng@nvidia.com>
> Signed-off-by: Shardar Mohammed <smohammed@nvidia.com>
> Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
> ---
> drivers/tty/serial/serial-tegra.c | 17 +++++++++++------
> 1 file changed, 11 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/tty/serial/serial-tegra.c b/drivers/tty/serial/serial-tegra.c
> index 93d299e..d908465 100644
> --- a/drivers/tty/serial/serial-tegra.c
> +++ b/drivers/tty/serial/serial-tegra.c
> @@ -126,6 +126,8 @@ struct tegra_uart_port {
>
> static void tegra_uart_start_next_tx(struct tegra_uart_port *tup);
> static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup);
> +static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,
> + bool dma_to_memory);
>
> static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup,
> unsigned long reg)
> @@ -458,6 +460,9 @@ static void tegra_uart_start_next_tx(struct tegra_uart_port *tup)
> unsigned long count;
> struct circ_buf *xmit = &tup->uport.state->xmit;
>
> + if (WARN_ON(!tup->current_baud))
> + return;
Are the race conditions that you are describing something which can be
triggered by the user? If so, it's not a good idea to use a WARN_ON,
because that could lead to some userspace spamming the log with these,
potentially on purpose.
Thierry
> +
> tail = (unsigned long)&xmit->buf[xmit->tail];
> count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
> if (!count)
> @@ -829,6 +834,12 @@ static void tegra_uart_hw_deinit(struct tegra_uart_port *tup)
> tup->current_baud = 0;
> spin_unlock_irqrestore(&tup->uport.lock, flags);
>
> + tup->rx_in_progress = 0;
> + tup->tx_in_progress = 0;
> +
> + tegra_uart_dma_channel_free(tup, true);
> + tegra_uart_dma_channel_free(tup, false);
> +
> clk_disable_unprepare(tup->uart_clk);
> }
>
> @@ -1066,12 +1077,6 @@ static void tegra_uart_shutdown(struct uart_port *u)
> struct tegra_uart_port *tup = to_tegra_uport(u);
>
> tegra_uart_hw_deinit(tup);
> -
> - tup->rx_in_progress = 0;
> - tup->tx_in_progress = 0;
> -
> - tegra_uart_dma_channel_free(tup, true);
> - tegra_uart_dma_channel_free(tup, false);
> free_irq(u->irq, tup);
> }
>
> --
> 2.7.4
>
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next prev parent reply other threads:[~2019-08-13 9:45 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-12 11:28 [PATCH 00/14] serial: tegra: Tegra186 support and fixes Krishna Yarlagadda
2019-08-12 11:28 ` [PATCH 01/14] serial: tegra: add internal loopback functionality Krishna Yarlagadda
2019-08-13 9:38 ` Thierry Reding
2019-08-12 11:28 ` [PATCH 02/14] serial: tegra: add support to ignore read Krishna Yarlagadda
2019-08-13 9:42 ` Thierry Reding
2019-08-27 9:29 ` Krishna Yarlagadda
2019-08-12 11:28 ` [PATCH 03/14] serial: tegra: avoid reg access when clk disabled Krishna Yarlagadda
2019-08-13 9:45 ` Thierry Reding [this message]
2019-08-27 9:29 ` Krishna Yarlagadda
2019-08-12 11:28 ` [PATCH 04/14] serial: tegra: protect IER against LCR.DLAB Krishna Yarlagadda
2019-08-13 9:46 ` Thierry Reding
2019-08-12 11:28 ` [PATCH 05/14] serial: tegra: flush the RX fifo on frame error Krishna Yarlagadda
2019-08-13 9:48 ` Thierry Reding
2019-08-27 9:29 ` Krishna Yarlagadda
2019-08-12 11:28 ` [PATCH 06/14] serial: tegra: report error to upper tty layer Krishna Yarlagadda
2019-08-13 9:52 ` Thierry Reding
2019-08-27 9:29 ` Krishna Yarlagadda
2019-08-12 11:28 ` [PATCH 07/14] serial: tegra: add compatible for new chips Krishna Yarlagadda
2019-08-13 9:55 ` Thierry Reding
2019-08-27 9:29 ` Krishna Yarlagadda
2019-08-12 11:28 ` [PATCH 08/14] serial: tegra: check for FIFO mode enabled status Krishna Yarlagadda
2019-08-13 10:03 ` Thierry Reding
2019-08-27 9:29 ` Krishna Yarlagadda
2019-08-12 11:28 ` [PATCH 09/14] serial: tegra: set maximum num of uart ports to 8 Krishna Yarlagadda
2019-08-13 10:19 ` Thierry Reding
2019-08-27 9:30 ` Krishna Yarlagadda
2019-08-12 11:28 ` [PATCH 10/14] serial: tegra: add support to use 8 bytes trigger Krishna Yarlagadda
2019-08-19 20:29 ` Jon Hunter
2019-08-27 9:31 ` Krishna Yarlagadda
2019-08-12 11:28 ` [PATCH 11/14] serial: tegra: DT for Adjusted baud rates Krishna Yarlagadda
2019-08-13 10:24 ` Thierry Reding
2019-08-27 9:31 ` Krishna Yarlagadda
2019-08-12 11:28 ` [PATCH 12/14] serial: tegra: add support to adjust baud rate Krishna Yarlagadda
2019-08-12 11:28 ` [PATCH 13/14] serial: tegra: report clk rate errors Krishna Yarlagadda
2019-08-12 11:28 ` [PATCH 14/14] serial: tegra: Add PIO mode support Krishna Yarlagadda
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