* [PATCH v4 0/2] Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support
@ 2022-05-04 9:44 Phil Edworthy
2022-05-04 9:44 ` [PATCH v4 1/2] dt-bindings: serial: renesas,em-uart: Add RZ/V2M clock to access the registers Phil Edworthy
0 siblings, 1 reply; 4+ messages in thread
From: Phil Edworthy @ 2022-05-04 9:44 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Greg Kroah-Hartman
Cc: Phil Edworthy, Biju Das, Lad Prabhakar, Chris Paterson,
linux-renesas-soc, devicetree, linux-clk, linux-serial,
linux-kernel
Hello,
RZ/V2M has a dual-core Cortex-A53 (1.0 GHz) CPU and built-in AI
accelerator "DRP-AI" for vision, which is Renesas' original technology.
It also has a 32-bit LPDDR4 interface and video codec (H.264).
The RZ/V2M is used with ISP firmware that runs on one of the Cortex-A53
cores. The firmware is an integral part of the SoC such that the HW
User's Manual documents which of the peripheral modules are used by the
firmware.
Initial patches enables minimal peripherals on Renesas RZ/V2M EVK board
and booted via nfs. Ethernet is broadly compatible with the
etheravb-rcar-gen3 driver, but interrupts need some work so it's not
been included in this patch set.
Below blocks are enabled on Renesas RZ/V2M EVK board:
- memory
- External input clock
- CPG
- UART
Links for SoC and EVK:
[*] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-cortex-a-mpus/rzv2m-dual-cortex-a53-lpddr4x32bit-ai-accelerator-isp-4k-video-codec-4k-camera-input-fhd-display-output
Sorry for cross posting the patches to multiple subsystems, as these are
just the dt-binding patches included as part of initial bringup patches.
v4:
* Removed arm,arch_timer optional clock and reset
* Removed "optional" from description of renesas,em-uart clock.
v3:
* Feedback addressed
* Added patch [0001] for renesas,em-uart dt-bindings RZ/V2M clock for the regs
* Added patch [0004] for arm,arch_timer dt-bindings optional clock and reset
* Added patch [0005] for rzg2l clk to move the DEF_MUX array size calc into the macro
* Added patch [0006] for rzg2l clk to add read-only versions of the macros
v2:
* Removed SYS dt-bindings patch and corresponding SoC identification
as we only used the LSI version register. This can be dealt with
later on.
* Fixed em-uart dt-bindings.
* Included reviewed-by tags.
Thanks
Phil
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v4 1/2] dt-bindings: serial: renesas,em-uart: Add RZ/V2M clock to access the registers
2022-05-04 9:44 [PATCH v4 0/2] Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support Phil Edworthy
@ 2022-05-04 9:44 ` Phil Edworthy
2022-05-11 15:03 ` Rob Herring
0 siblings, 1 reply; 4+ messages in thread
From: Phil Edworthy @ 2022-05-04 9:44 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Geert Uytterhoeven
Cc: Phil Edworthy, Magnus Damm, Biju Das, linux-renesas-soc,
linux-serial, devicetree
The RZ/V2M SoC has an additional clock to access the registers. The HW
manual says this clock should not be touched as it is used by the
"ISP Firmware".
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v4:
- Removed "optional" from description of clock to access the registers
v3:
- New patch added
---
.../bindings/serial/renesas,em-uart.yaml | 32 +++++++++++++++----
1 file changed, 25 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
index 332c385618e1..40a03f255666 100644
--- a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
@@ -9,9 +9,6 @@ title: Renesas EMMA Mobile UART Interface
maintainers:
- Magnus Damm <magnus.damm@gmail.com>
-allOf:
- - $ref: serial.yaml#
-
properties:
compatible:
oneOf:
@@ -29,11 +26,32 @@ properties:
interrupts:
maxItems: 1
- clocks:
- maxItems: 1
+allOf:
+ - $ref: serial.yaml#
- clock-names:
- const: sclk
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a09g011-uart
+ then:
+ properties:
+ clocks:
+ items:
+ - description: UART functional clock
+ - description: Internal clock to access the registers
+ clock-names:
+ items:
+ - const: sclk
+ - const: pclk
+ else:
+ properties:
+ clocks:
+ items:
+ - description: UART functional clock
+ clock-names:
+ items:
+ - const: sclk
required:
- compatible
--
2.32.0
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH v4 1/2] dt-bindings: serial: renesas,em-uart: Add RZ/V2M clock to access the registers
2022-05-04 9:44 ` [PATCH v4 1/2] dt-bindings: serial: renesas,em-uart: Add RZ/V2M clock to access the registers Phil Edworthy
@ 2022-05-11 15:03 ` Rob Herring
2022-05-12 7:04 ` Phil Edworthy
0 siblings, 1 reply; 4+ messages in thread
From: Rob Herring @ 2022-05-11 15:03 UTC (permalink / raw)
To: Phil Edworthy
Cc: Greg Kroah-Hartman, Krzysztof Kozlowski, Geert Uytterhoeven,
Magnus Damm, Biju Das, linux-renesas-soc, linux-serial,
devicetree
On Wed, May 04, 2022 at 10:44:55AM +0100, Phil Edworthy wrote:
> The RZ/V2M SoC has an additional clock to access the registers. The HW
> manual says this clock should not be touched as it is used by the
> "ISP Firmware".
>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> v4:
> - Removed "optional" from description of clock to access the registers
> v3:
> - New patch added
> ---
> .../bindings/serial/renesas,em-uart.yaml | 32 +++++++++++++++----
> 1 file changed, 25 insertions(+), 7 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> index 332c385618e1..40a03f255666 100644
> --- a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> +++ b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> @@ -9,9 +9,6 @@ title: Renesas EMMA Mobile UART Interface
> maintainers:
> - Magnus Damm <magnus.damm@gmail.com>
>
> -allOf:
> - - $ref: serial.yaml#
> -
> properties:
> compatible:
> oneOf:
> @@ -29,11 +26,32 @@ properties:
> interrupts:
> maxItems: 1
>
> - clocks:
> - maxItems: 1
> +allOf:
> + - $ref: serial.yaml#
>
> - clock-names:
> - const: sclk
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: renesas,r9a09g011-uart
> + then:
> + properties:
> + clocks:
> + items:
> + - description: UART functional clock
> + - description: Internal clock to access the registers
> + clock-names:
> + items:
> + - const: sclk
> + - const: pclk
Better to put all this at the top level with 'minItems: 1' and then use
minItems/maxItems in the if/then schema to define which platforms have 1
or 2 clocks.
> + else:
> + properties:
> + clocks:
> + items:
> + - description: UART functional clock
> + clock-names:
> + items:
> + - const: sclk
>
> required:
> - compatible
> --
> 2.32.0
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* RE: [PATCH v4 1/2] dt-bindings: serial: renesas,em-uart: Add RZ/V2M clock to access the registers
2022-05-11 15:03 ` Rob Herring
@ 2022-05-12 7:04 ` Phil Edworthy
0 siblings, 0 replies; 4+ messages in thread
From: Phil Edworthy @ 2022-05-12 7:04 UTC (permalink / raw)
To: Rob Herring
Cc: Greg Kroah-Hartman, Krzysztof Kozlowski, Geert Uytterhoeven,
Magnus Damm, Biju Das, linux-renesas-soc@vger.kernel.org,
linux-serial@vger.kernel.org, devicetree@vger.kernel.org
Hi Rob,
On 11 May 2022 16:04 Rob Herring wrote:
> On Wed, May 04, 2022 at 10:44:55AM +0100, Phil Edworthy wrote:
> > The RZ/V2M SoC has an additional clock to access the registers. The HW
> > manual says this clock should not be touched as it is used by the
> > "ISP Firmware".
> >
> > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > ---
> > v4:
> > - Removed "optional" from description of clock to access the registers
> > v3:
> > - New patch added
> > ---
> > .../bindings/serial/renesas,em-uart.yaml | 32 +++++++++++++++----
> > 1 file changed, 25 insertions(+), 7 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/serial/renesas,em-
> uart.yaml b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> > index 332c385618e1..40a03f255666 100644
> > --- a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> > +++ b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> > @@ -9,9 +9,6 @@ title: Renesas EMMA Mobile UART Interface
> > maintainers:
> > - Magnus Damm <magnus.damm@gmail.com>
> >
> > -allOf:
> > - - $ref: serial.yaml#
> > -
> > properties:
> > compatible:
> > oneOf:
> > @@ -29,11 +26,32 @@ properties:
> > interrupts:
> > maxItems: 1
> >
> > - clocks:
> > - maxItems: 1
> > +allOf:
> > + - $ref: serial.yaml#
> >
> > - clock-names:
> > - const: sclk
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: renesas,r9a09g011-uart
> > + then:
> > + properties:
>
> > + clocks:
> > + items:
> > + - description: UART functional clock
> > + - description: Internal clock to access the registers
> > + clock-names:
> > + items:
> > + - const: sclk
> > + - const: pclk
>
> Better to put all this at the top level with 'minItems: 1' and then use
> minItems/maxItems in the if/then schema to define which platforms have 1
> or 2 clocks.
Thanks Rob, will do!
Phil
> > + else:
> > + properties:
> > + clocks:
> > + items:
> > + - description: UART functional clock
> > + clock-names:
> > + items:
> > + - const: sclk
> >
> > required:
> > - compatible
> > --
> > 2.32.0
> >
> >
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-05-12 7:04 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2022-05-04 9:44 [PATCH v4 0/2] Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support Phil Edworthy
2022-05-04 9:44 ` [PATCH v4 1/2] dt-bindings: serial: renesas,em-uart: Add RZ/V2M clock to access the registers Phil Edworthy
2022-05-11 15:03 ` Rob Herring
2022-05-12 7:04 ` Phil Edworthy
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