From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1E9AC433F5 for ; Tue, 17 May 2022 11:08:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343864AbiEQLI5 (ORCPT ); Tue, 17 May 2022 07:08:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49418 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345018AbiEQLI2 (ORCPT ); Tue, 17 May 2022 07:08:28 -0400 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8887C192B4; Tue, 17 May 2022 04:08:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652785705; x=1684321705; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=B/wsivre0Bc6qlbjo3she/qQCDt/pTlKU20VjyLCa68=; b=BG6hiY8acAju7sKaUALXT6bROQfAhPXQg8r1SIvJaQdA4nXmzxftiTGg bwN+bZ2hiWKjz1RslGvGnPm7tJx0dysqDPeZ9NG37L7evUSLHtlYjPmY4 yOCoC7oIHq8emOFu2lBu4RYSw7GAVC+GQsSxxRLVfofo35v7K0ftFkGMK 24+W4POrTsGfH/ExC1Mj+HwowbTOtH9nKcnAyHgXrtLXQ0qd4DaVqaJwY 5718a5/J7lQ9LnDMYn5mqypqn1LEj1f34fFdphUNOo9u4MV3FHsh/TnJw wNKHDqxUWV13jxmrlMVwAJUHY7Gqlomd3KPPy00kNxknQWcaydO4D4cwD w==; X-IronPort-AV: E=McAfee;i="6400,9594,10349"; a="271268787" X-IronPort-AV: E=Sophos;i="5.91,232,1647327600"; d="scan'208";a="271268787" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 May 2022 04:08:25 -0700 X-IronPort-AV: E=Sophos;i="5.91,232,1647327600"; d="scan'208";a="568831136" Received: from mtarral-mobl.ger.corp.intel.com (HELO ijarvine-MOBL2.ger.corp.intel.com) ([10.252.52.88]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 May 2022 04:08:22 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-serial@vger.kernel.org, Greg KH , Jiri Slaby , Maxime Coquelin , Alexandre Torgue , Erwan Le Ray , linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 8/9] serial: stm32-usart: Correct CSIZE, bits, and parity Date: Tue, 17 May 2022 14:07:36 +0300 Message-Id: <20220517110737.37148-9-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220517110737.37148-1-ilpo.jarvinen@linux.intel.com> References: <20220517110737.37148-1-ilpo.jarvinen@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Add CSIZE sanitization for unsupported CSIZE configurations. In addition, if parity is asked for but CSx was unsupported, the sensible result is CS8+parity which requires setting USART_CR1_M0 like with 9 bits. Incorrect CSIZE results in miscalculation of the frame bits in tty_get_char_size() or in its predecessor where the roughly the same code is directly within uart_update_timeout(). Cc: Erwan Le Ray Fixes: c8a9d043947b (serial: stm32: fix word length configuration) Signed-off-by: Ilpo Järvinen --- drivers/tty/serial/stm32-usart.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/tty/serial/stm32-usart.c b/drivers/tty/serial/stm32-usart.c index 87b5cd4c9743..3c551fd4f3ff 100644 --- a/drivers/tty/serial/stm32-usart.c +++ b/drivers/tty/serial/stm32-usart.c @@ -1037,13 +1037,22 @@ static void stm32_usart_set_termios(struct uart_port *port, * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00 * M0 and M1 already cleared by cr1 initialization. */ - if (bits == 9) + if (bits == 9) { cr1 |= USART_CR1_M0; - else if ((bits == 7) && cfg->has_7bits_data) + } else if ((bits == 7) && cfg->has_7bits_data) { cr1 |= USART_CR1_M1; - else if (bits != 8) + } else if (bits != 8) { dev_dbg(port->dev, "Unsupported data bits config: %u bits\n" , bits); + cflag &= ~CSIZE; + cflag |= CS8; + termios->c_cflag = cflag; + bits = 8; + if (cflag & PARENB) { + bits++; + cr1 |= USART_CR1_M0; + } + } if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch || (stm32_port->fifoen && -- 2.30.2