[PATCH v2 0/9] riscv: add Bouffalolab bl808 support

[PATCH v2 0/9] riscv: add Bouffalolab bl808 support

[Jisheng Zhang]

This series adds Bouffalolab uart driver and basic devicetrees for
Bouffalolab bl808 SoC and Sipeed M1s dock board.

It's too late for v6.2-rc1, but I hope I can catch up the v6.3-rc1
window.

I think I have addressed all review comments to v1, correct me if I
missed anything.

PS: this series assumes the "thead,c906" riscv cpu binding patch is
merged(I see Conor has picked up it).

Since v1:
  - use FIELD_PREP and FIELD_GET macro
  - rewrite bflb_uart_tx_chars()
  - add vendor prefix for bouffalolab
  - add dt binding for bl808 compatibles
  - enable SOC_BOUFFALOLAB in defconfig
  - collect Reviewed-by tag
  - modify commit-msg as suggested

Jisheng Zhang (9):
  dt-bindings: serial: add documentation for Bouffalolab UART Driver
  serial: bflb_uart: add Bouffalolab UART Driver
  riscv: add the Bouffalolab SoC family Kconfig option
  dt-bindings: vendor-prefixes: add bouffalolab
  dt-bindings: riscv: Add bouffalolab bl808 board compatibles
  riscv: dts: bouffalolab: add the bl808 SoC base device tree
  riscv: dts: bouffalolab: add Sipeed M1s SoM and Dock devicetree
  MAINTAINERS: riscv: add entry for Bouffalolab SoC
  riscv: defconfig: enable BOUFFALOLAB SoC

 .../bindings/riscv/bouffalolab.yaml           |  34 +
 .../bindings/serial/bouffalolab,uart.yaml     |  47 ++
 .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
 MAINTAINERS                                   |   9 +
 arch/riscv/Kconfig.socs                       |   6 +
 arch/riscv/boot/dts/Makefile                  |   1 +
 arch/riscv/boot/dts/bouffalolab/Makefile      |   2 +
 .../dts/bouffalolab/bl808-sipeed-m1s-dock.dts |  25 +
 .../dts/bouffalolab/bl808-sipeed-m1s.dtsi     |  21 +
 arch/riscv/boot/dts/bouffalolab/bl808.dtsi    |  74 +++
 arch/riscv/configs/defconfig                  |   1 +
 drivers/tty/serial/Kconfig                    |  18 +
 drivers/tty/serial/Makefile                   |   1 +
 drivers/tty/serial/bflb_uart.c                | 610 ++++++++++++++++++
 include/uapi/linux/serial_core.h              |   3 +
 15 files changed, 854 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/bouffalolab.yaml
 create mode 100644 Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml
 create mode 100644 arch/riscv/boot/dts/bouffalolab/Makefile
 create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s-dock.dts
 create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dtsi
 create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi
 create mode 100644 drivers/tty/serial/bflb_uart.c

-- 
2.38.1

[PATCH v2 1/9] dt-bindings: serial: add documentation for Bouffalolab UART Driver

[Jisheng Zhang]

Add bindings doc for Bouffalolab UART Driver

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
 .../bindings/serial/bouffalolab,uart.yaml     | 47 +++++++++++++++++++
 1 file changed, 47 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml

diff --git a/Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml b/Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml
new file mode 100644
index 000000000000..a8293444ca31
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/serial/bouffalolab,uart.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bouffalolab UART Controller
+
+maintainers:
+  - Jisheng Zhang <jszhang@kernel.org>
+
+allOf:
+  - $ref: serial.yaml#
+
+properties:
+  compatible:
+    const: bouffalolab,bl808-uart
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    uart0: serial@30002000 {
+        compatible = "bouffalolab,bl808-uart";
+        reg = <0x30002000 0x1000>;
+        interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&xtal>;
+    };
+...
-- 
2.38.1

[PATCH v2 2/9] serial: bflb_uart: add Bouffalolab UART Driver

[Jisheng Zhang]

Add the driver for Bouffalolab UART IP which is found in Bouffalolab
SoCs such as bl808.

UART driver probe will create path named "/dev/ttySx".

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
 drivers/tty/serial/Kconfig       |  18 +
 drivers/tty/serial/Makefile      |   1 +
 drivers/tty/serial/bflb_uart.c   | 610 +++++++++++++++++++++++++++++++
 include/uapi/linux/serial_core.h |   3 +
 4 files changed, 632 insertions(+)
 create mode 100644 drivers/tty/serial/bflb_uart.c

diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 434f83168546..056a8144e2cc 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -179,6 +179,24 @@ config SERIAL_ATMEL_TTYAT
 
 	  Say Y if you have an external 8250/16C550 UART.  If unsure, say N.
 
+config SERIAL_BFLB
+	tristate "Bouffalolab serial port support"
+	select SERIAL_CORE
+	depends on COMMON_CLK
+	help
+	  This enables the driver for the Bouffalolab's serial.
+
+config SERIAL_BFLB_CONSOLE
+	bool "Support for console on Bouffalolab serial port"
+	depends on SERIAL_BFLB
+	select SERIAL_CORE_CONSOLE
+	select SERIAL_EARLYCON
+	help
+	  Say Y here if you wish to use a Bouffalolab UART as the
+	  system console (the system console is the device which
+	  receives all kernel messages and warnings and which allows
+	  logins in single user mode) as /dev/ttySn.
+
 config SERIAL_KGDB_NMI
 	bool "Serial console over KGDB NMI debugger port"
 	depends on KGDB_SERIAL_CONSOLE
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index 238a9557b487..8509cdc11d87 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_SERIAL_8250) += 8250/
 
 obj-$(CONFIG_SERIAL_AMBA_PL010) += amba-pl010.o
 obj-$(CONFIG_SERIAL_AMBA_PL011) += amba-pl011.o
+obj-$(CONFIG_SERIAL_BFLB) += bflb_uart.o
 obj-$(CONFIG_SERIAL_CLPS711X) += clps711x.o
 obj-$(CONFIG_SERIAL_PXA_NON8250) += pxa.o
 obj-$(CONFIG_SERIAL_SA1100) += sa1100.o
diff --git a/drivers/tty/serial/bflb_uart.c b/drivers/tty/serial/bflb_uart.c
new file mode 100644
index 000000000000..1816c5c71cae
--- /dev/null
+++ b/drivers/tty/serial/bflb_uart.c
@@ -0,0 +1,610 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Based on bflb_uart.c, by Bouffalolab team
+ *
+ * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/console.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+
+#define UART_UTX_CONFIG			0x00
+#define  UART_CR_UTX_EN			BIT(0)
+#define  UART_CR_UTX_CTS_EN		BIT(1)
+#define  UART_CR_UTX_FRM_EN		BIT(2)
+#define  UART_CR_UTX_PRT_EN		BIT(4)
+#define  UART_CR_UTX_PRT_SEL		BIT(5)
+#define  UART_CR_UTX_BIT_CNT_D_MSK	GENMASK(10, 8)
+#define  UART_CR_UTX_BIT_CNT_P_MSK	GENMASK(12, 11)
+#define UART_URX_CONFIG			0x04
+#define  UART_CR_URX_EN			BIT(0)
+#define  UART_CR_URX_PRT_EN		BIT(4)
+#define  UART_CR_URX_PRT_SEL		BIT(5)
+#define  UART_CR_URX_BIT_CNT_D_MSK	GENMASK(10, 8)
+#define UART_BIT_PRD			0x08
+#define  UART_CR_UTX_BIT_PRD_MSK	GENMASK(15, 0)
+#define  UART_CR_URX_BIT_PRD_MSK	GENMASK(31, 16)
+#define UART_DATA_CONFIG		0x0c
+#define  UART_CR_UART_BIT_INV		BIT(0)
+#define UART_URX_RTO_TIMER		0x18
+#define  UART_CR_URX_RTO_VALUE_MSK	GENMASK(7, 0)
+#define UART_SW_MODE			0x1c
+#define UART_INT_STS			0x20
+#define  UART_UTX_END_INT		BIT(0)
+#define  UART_URX_END_INT		BIT(1)
+#define  UART_UTX_FIFO_INT		BIT(2)
+#define  UART_URX_FIFO_INT		BIT(3)
+#define  UART_URX_RTO_INT		BIT(4)
+#define  UART_URX_PCE_INT		BIT(5)
+#define  UART_UTX_FER_INT		BIT(6)
+#define  UART_URX_FER_INT		BIT(7)
+#define  UART_URX_LSE_INT		BIT(8)
+#define UART_INT_MASK			0x24
+#define UART_INT_CLEAR			0x28
+#define UART_INT_EN			0x2c
+#define UART_STATUS			0x30
+#define  UART_STS_UTX_BUS_BUSY		BIT(0)
+#define UART_FIFO_CONFIG_0		0x80
+#define  UART_DMA_TX_EN			BIT(0)
+#define  UART_DMA_RX_EN			BIT(1)
+#define  UART_TX_FIFO_CLR		BIT(2)
+#define  UART_RX_FIFO_CLR		BIT(3)
+#define  UART_TX_FIFO_OVERFLOW		BIT(4)
+#define  UART_TX_FIFO_UNDERFLOW		BIT(5)
+#define  UART_RX_FIFO_OVERFLOW		BIT(6)
+#define  UART_RX_FIFO_UNDERFLOW		BIT(7)
+#define UART_FIFO_CONFIG_1		0x84
+#define  UART_TX_FIFO_CNT_MSK		GENMASK(5, 0)
+#define  UART_RX_FIFO_CNT_MSK		GENMASK(13, 8)
+#define  UART_TX_FIFO_TH_MSK		GENMASK(20, 16)
+#define  UART_RX_FIFO_TH_MSK		GENMASK(28, 24)
+#define UART_FIFO_WDATA			0x88
+#define UART_FIFO_RDATA			0x8c
+#define  UART_FIFO_RDATA_MSK		GENMASK(7, 0)
+
+#define BFLB_UART_MAXPORTS		8
+#define BFLB_UART_BAUD			2000000
+#define BFLB_UART_RX_FIFO_TH		7
+#define BFLB_UART_TX_FIFO_TH		15
+#define BFLB_UART_URX_RTO_TIME		0x4f
+
+struct bflb_uart_port {
+	struct uart_port port;
+	struct clk *clk;
+};
+
+static struct bflb_uart_port *bflb_uart_ports[BFLB_UART_MAXPORTS];
+
+static inline u32 rdl(struct uart_port *port, u32 reg)
+{
+	return readl_relaxed(port->membase + reg);
+}
+
+static inline void wrl(struct uart_port *port, u32 reg, u32 value)
+{
+	writel_relaxed(value, port->membase + reg);
+}
+
+static inline void wrb(struct uart_port *port, u32 reg, u8 value)
+{
+	writeb_relaxed(value, port->membase + reg);
+}
+
+static unsigned int bflb_uart_tx_empty(struct uart_port *port)
+{
+	return (rdl(port, UART_FIFO_CONFIG_1) & UART_TX_FIFO_CNT_MSK) ? TIOCSER_TEMT : 0;
+}
+
+static unsigned int bflb_uart_get_mctrl(struct uart_port *port)
+{
+	return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
+}
+
+static void bflb_uart_set_mctrl(struct uart_port *port, unsigned int sigs)
+{
+}
+
+static void bflb_uart_start_tx(struct uart_port *port)
+{
+	u32 val;
+
+	val = rdl(port, UART_UTX_CONFIG);
+	val |= UART_CR_UTX_EN;
+	wrl(port, UART_UTX_CONFIG, val);
+
+	val = rdl(port, UART_FIFO_CONFIG_1);
+	val &= ~UART_TX_FIFO_TH_MSK;
+	val |= FIELD_PREP(UART_TX_FIFO_TH_MSK, BFLB_UART_TX_FIFO_TH);
+	wrl(port, UART_FIFO_CONFIG_1, val);
+
+	val = rdl(port, UART_INT_MASK);
+	val &= ~UART_UTX_FIFO_INT;
+	wrl(port, UART_INT_MASK, val);
+}
+
+static void bflb_uart_stop_tx(struct uart_port *port)
+{
+	u32 val;
+
+	val = rdl(port, UART_INT_MASK);
+	val |= UART_UTX_FIFO_INT;
+	wrl(port, UART_INT_MASK, val);
+}
+
+static void bflb_uart_stop_rx(struct uart_port *port)
+{
+	u32 val;
+
+	val = rdl(port, UART_URX_CONFIG);
+	val &= ~UART_CR_URX_EN;
+	wrl(port, UART_URX_CONFIG, val);
+
+	val = rdl(port, UART_INT_MASK);
+	val |= UART_URX_FIFO_INT | UART_URX_RTO_INT | UART_URX_FER_INT;
+	wrl(port, UART_INT_MASK, val);
+}
+
+static void bflb_uart_set_termios(struct uart_port *port,
+				  struct ktermios *termios,
+				  const struct ktermios *old)
+{
+	unsigned long flags;
+	u32 valt, valr, val;
+	unsigned int baud, min;
+
+	spin_lock_irqsave(&port->lock, flags);
+
+	/* set data length */
+	val = tty_get_char_size(termios->c_cflag) - 1;
+	valt = FIELD_PREP(UART_CR_UTX_BIT_CNT_D_MSK, val);
+
+	/* calculate parity */
+	termios->c_cflag &= ~CMSPAR;	/* no support mark/space */
+	if (termios->c_cflag & PARENB) {
+		valt |= UART_CR_UTX_PRT_EN;
+		if (termios->c_cflag & PARODD)
+			valt |= UART_CR_UTX_PRT_SEL;
+	}
+
+	valr = valt;
+
+	/* calculate stop bits */
+	if (termios->c_cflag & CSTOPB)
+		val = 2;
+	else
+		val = 1;
+	valt |= FIELD_PREP(UART_CR_UTX_BIT_CNT_P_MSK, val);
+
+	/* flow control */
+	if (termios->c_cflag & CRTSCTS)
+		valt |= UART_CR_UTX_CTS_EN;
+
+	/* enable TX freerunning mode */
+	valt |= UART_CR_UTX_FRM_EN;
+
+	valt |= UART_CR_UTX_EN;
+	valr |= UART_CR_URX_EN;
+
+	wrl(port, UART_UTX_CONFIG, valt);
+	wrl(port, UART_URX_CONFIG, valr);
+
+	min = port->uartclk / (UART_CR_UTX_BIT_PRD_MSK + 1);
+	baud = uart_get_baud_rate(port, termios, old, min, 4000000);
+
+	val = DIV_ROUND_CLOSEST(port->uartclk, baud) - 1;
+	val = FIELD_PREP(UART_CR_UTX_BIT_PRD_MSK, val);
+	val |= FIELD_PREP(UART_CR_URX_BIT_PRD_MSK, val);
+	wrl(port, UART_BIT_PRD, val);
+
+	uart_update_timeout(port, termios->c_cflag, baud);
+
+	spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static void bflb_uart_rx_chars(struct uart_port *port)
+{
+	u8 ch;
+
+	while (rdl(port, UART_FIFO_CONFIG_1) & UART_RX_FIFO_CNT_MSK) {
+		ch = FIELD_GET(UART_FIFO_RDATA_MSK, rdl(port, UART_FIFO_RDATA));
+		port->icount.rx++;
+
+		if (uart_handle_sysrq_char(port, ch))
+			continue;
+		uart_insert_char(port, 0, 0, ch, TTY_NORMAL);
+	}
+
+	spin_unlock(&port->lock);
+	tty_flip_buffer_push(&port->state->port);
+	spin_lock(&port->lock);
+}
+
+static void bflb_uart_tx_chars(struct uart_port *port)
+{
+	struct circ_buf *xmit = &port->state->xmit;
+	unsigned int count;
+
+	if (port->x_char) {
+		/* Send special char - probably flow control */
+		wrl(port, UART_FIFO_WDATA, port->x_char);
+		port->x_char = 0;
+		port->icount.tx++;
+		return;
+	}
+
+	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
+		bflb_uart_stop_tx(port);
+		return;
+	}
+
+	count = BFLB_UART_TX_FIFO_TH;
+	do {
+		wrl(port, UART_FIFO_WDATA, xmit->buf[xmit->tail]);
+		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+		port->icount.tx++;
+		if (uart_circ_empty(xmit))
+			break;
+	} while (--count > 0);
+
+	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+		uart_write_wakeup(port);
+
+	if (uart_circ_empty(xmit))
+		bflb_uart_stop_tx(port);
+}
+
+static irqreturn_t bflb_uart_interrupt(int irq, void *data)
+{
+	struct uart_port *port = data;
+	u32 isr, val;
+
+	isr = rdl(port, UART_INT_STS);
+	wrl(port, UART_INT_CLEAR, isr);
+
+	spin_lock(&port->lock);
+
+	if (isr & UART_URX_FER_INT) {
+		/* RX FIFO error interrupt */
+		val = rdl(port, UART_FIFO_CONFIG_0);
+		if (val & UART_RX_FIFO_OVERFLOW)
+			port->icount.overrun++;
+
+		val |= UART_RX_FIFO_CLR;
+		wrl(port, UART_FIFO_CONFIG_0, val);
+	}
+
+	if (isr & (UART_URX_FIFO_INT | UART_URX_RTO_INT))
+		bflb_uart_rx_chars(port);
+
+	if (isr & UART_UTX_FIFO_INT)
+		bflb_uart_tx_chars(port);
+
+	spin_unlock(&port->lock);
+
+	return IRQ_RETVAL(isr);
+}
+
+static void bflb_uart_config_port(struct uart_port *port, int flags)
+{
+	port->type = PORT_BFLB;
+}
+
+static int bflb_uart_startup(struct uart_port *port)
+{
+	unsigned long flags;
+	int ret;
+	u32 val;
+
+	ret = devm_request_irq(port->dev, port->irq, bflb_uart_interrupt,
+			       IRQF_SHARED, port->name, port);
+	if (ret) {
+		dev_err(port->dev, "fail to request serial irq %d, ret=%d\n",
+			port->irq, ret);
+		return ret;
+	}
+
+	spin_lock_irqsave(&port->lock, flags);
+
+	wrl(port, UART_INT_MASK, ~0);
+
+	wrl(port, UART_DATA_CONFIG, 0);
+	wrl(port, UART_SW_MODE, 0);
+	wrl(port, UART_URX_RTO_TIMER, FIELD_PREP(UART_CR_URX_RTO_VALUE_MSK, BFLB_UART_URX_RTO_TIME));
+
+	val = rdl(port, UART_FIFO_CONFIG_1);
+	val &= ~UART_RX_FIFO_TH_MSK;
+	val |= FIELD_PREP(UART_RX_FIFO_TH_MSK, BFLB_UART_RX_FIFO_TH);
+	wrl(port, UART_FIFO_CONFIG_1, val);
+
+	/* Unmask RX interrupts now */
+	val = rdl(port, UART_INT_MASK);
+	val &= ~(UART_URX_FIFO_INT | UART_URX_RTO_INT | UART_URX_FER_INT);
+	wrl(port, UART_INT_MASK, val);
+
+	val = rdl(port, UART_UTX_CONFIG);
+	val |= UART_CR_UTX_EN;
+	wrl(port, UART_UTX_CONFIG, val);
+	val = rdl(port, UART_URX_CONFIG);
+	val |= UART_CR_URX_EN;
+	wrl(port, UART_URX_CONFIG, val);
+
+	spin_unlock_irqrestore(&port->lock, flags);
+
+	return 0;
+}
+
+static void bflb_uart_shutdown(struct uart_port *port)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&port->lock, flags);
+	/* mask all interrupts now */
+	wrl(port, UART_INT_MASK, ~0);
+	spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static const char *bflb_uart_type(struct uart_port *port)
+{
+	return (port->type == PORT_BFLB) ? "BFLB UART" : NULL;
+}
+
+static int bflb_uart_verify_port(struct uart_port *port,
+				 struct serial_struct *ser)
+{
+	if (ser->type != PORT_UNKNOWN && ser->type != PORT_BFLB)
+		return -EINVAL;
+	return 0;
+}
+
+static const struct uart_ops bflb_uart_ops = {
+	.tx_empty = bflb_uart_tx_empty,
+	.get_mctrl = bflb_uart_get_mctrl,
+	.set_mctrl = bflb_uart_set_mctrl,
+	.start_tx = bflb_uart_start_tx,
+	.stop_tx = bflb_uart_stop_tx,
+	.stop_rx = bflb_uart_stop_rx,
+	.startup = bflb_uart_startup,
+	.shutdown = bflb_uart_shutdown,
+	.set_termios = bflb_uart_set_termios,
+	.type = bflb_uart_type,
+	.config_port = bflb_uart_config_port,
+	.verify_port = bflb_uart_verify_port,
+};
+
+#ifdef CONFIG_SERIAL_BFLB_CONSOLE
+static void bflb_console_putchar(struct uart_port *port, unsigned char ch)
+{
+	while (!(rdl(port, UART_FIFO_CONFIG_1) & UART_TX_FIFO_CNT_MSK))
+		cpu_relax();
+	wrb(port, UART_FIFO_WDATA, ch);
+}
+
+/*
+ * Interrupts are disabled on entering
+ */
+static void bflb_uart_console_write(struct console *co, const char *s,
+				    u_int count)
+{
+	struct uart_port *port = &bflb_uart_ports[co->index]->port;
+	u32 status, reg, mask;
+
+	/* save then disable interrupts */
+	mask = rdl(port, UART_INT_MASK);
+	reg = ~0;
+	wrl(port, UART_INT_MASK, reg);
+
+	/* Make sure that tx is enabled */
+	reg = rdl(port, UART_UTX_CONFIG);
+	reg |= UART_CR_UTX_EN;
+	wrl(port, UART_UTX_CONFIG, reg);
+
+	uart_console_write(port, s, count, bflb_console_putchar);
+
+	/* wait for TX done */
+	do {
+		status = rdl(port, UART_STATUS);
+	} while ((status & UART_STS_UTX_BUS_BUSY));
+
+	/* restore IRQ mask */
+	wrl(port, UART_INT_MASK, mask);
+}
+
+static int bflb_uart_console_setup(struct console *co, char *options)
+{
+	struct uart_port *port;
+	struct bflb_uart_port *bp;
+	int baud = BFLB_UART_BAUD;
+	int bits = 8;
+	int parity = 'n';
+	int flow = 'n';
+	u32 val;
+
+	if (co->index >= BFLB_UART_MAXPORTS || co->index < 0)
+		return -EINVAL;
+
+	bp = bflb_uart_ports[co->index];
+	if (!bp)
+		/* Port not initialized yet - delay setup */
+		return -ENODEV;
+
+	port = &bp->port;
+
+	val = rdl(port, UART_UTX_CONFIG);
+	val |= UART_CR_UTX_EN;
+	wrl(port, UART_UTX_CONFIG, val);
+
+	if (options)
+		uart_parse_options(options, &baud, &parity, &bits, &flow);
+
+	return uart_set_options(port, co, baud, parity, bits, flow);
+}
+
+static struct uart_driver bflb_uart_driver;
+static struct console bflb_uart_console = {
+	.name = "ttyS",
+	.write = bflb_uart_console_write,
+	.device = uart_console_device,
+	.setup = bflb_uart_console_setup,
+	.flags = CON_PRINTBUFFER,
+	.index = -1,
+	.data = &bflb_uart_driver,
+};
+
+static int __init bflb_uart_console_init(void)
+{
+	register_console(&bflb_uart_console);
+	return 0;
+}
+console_initcall(bflb_uart_console_init);
+
+#define BFLB_UART_CONSOLE (&bflb_uart_console)
+
+static void bflb_uart_earlycon_write(struct console *co, const char *s,
+				     unsigned int count)
+{
+	struct earlycon_device *dev = co->data;
+
+	uart_console_write(&dev->port, s, count, bflb_console_putchar);
+}
+
+static int __init bflb_uart_earlycon_setup(struct earlycon_device *dev,
+					   const char *options)
+{
+	if (!dev->port.membase)
+		return -ENODEV;
+
+	dev->con->write = bflb_uart_earlycon_write;
+
+	return 0;
+}
+OF_EARLYCON_DECLARE(bflb_uart, "bouffalolab,uart", bflb_uart_earlycon_setup);
+
+#else
+
+#define BFLB_UART_CONSOLE NULL
+
+#endif /* CONFIG_SERIAL_BFLB_CONSOLE */
+
+static struct uart_driver bflb_uart_driver = {
+	.owner = THIS_MODULE,
+	.driver_name = "bflb_uart",
+	.dev_name = "ttyS",
+	.nr = BFLB_UART_MAXPORTS,
+	.cons = BFLB_UART_CONSOLE,
+};
+
+static int bflb_uart_probe(struct platform_device *pdev)
+{
+	struct uart_port *port;
+	struct bflb_uart_port *bp;
+	struct resource *res;
+	int index, irq;
+
+	index = of_alias_get_id(pdev->dev.of_node, "serial");
+	if (unlikely(index < 0 || index >= BFLB_UART_MAXPORTS)) {
+		dev_err(&pdev->dev, "got a wrong serial alias id %d\n", index);
+		return -EINVAL;
+	}
+
+	bp = devm_kzalloc(&pdev->dev, sizeof(*bp), GFP_KERNEL);
+	if (!bp)
+		return -ENOMEM;
+
+	bflb_uart_ports[index] = bp;
+	platform_set_drvdata(pdev, bp);
+	port = &bp->port;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	port->membase = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(port->membase))
+		return PTR_ERR(port->membase);
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0)
+		return irq;
+
+	port->mapbase = res->start;
+	port->irq = irq;
+	port->line = index;
+	port->type = PORT_BFLB;
+	port->iotype = UPIO_MEM;
+	port->fifosize = 32;
+	port->ops = &bflb_uart_ops;
+	port->flags = UPF_BOOT_AUTOCONF;
+	port->dev = &pdev->dev;
+	port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_BFLB_CONSOLE);
+
+	bp->clk = devm_clk_get_enabled(&pdev->dev, NULL);
+	if (IS_ERR(bp->clk))
+		return PTR_ERR(bp->clk);
+	port->uartclk = clk_get_rate(bp->clk);
+
+	return uart_add_one_port(&bflb_uart_driver, port);
+}
+
+static int bflb_uart_remove(struct platform_device *pdev)
+{
+	struct bflb_uart_port *bp = platform_get_drvdata(pdev);
+
+	uart_remove_one_port(&bflb_uart_driver, &bp->port);
+	bflb_uart_ports[bp->port.line] = NULL;
+
+	return 0;
+}
+
+static const struct of_device_id bflb_uart_match[] = {
+	{
+		.compatible = "bouffalolab,bl808-uart",
+	},
+	{},
+};
+MODULE_DEVICE_TABLE(of, bflb_uart_match);
+
+static struct platform_driver bflb_uart_platform_driver = {
+	.probe	= bflb_uart_probe,
+	.remove	= bflb_uart_remove,
+	.driver	= {
+		.name		= "bflb_uart",
+		.of_match_table	= of_match_ptr(bflb_uart_match),
+	},
+};
+
+static int __init bflb_uart_init(void)
+{
+	int ret;
+
+	ret = uart_register_driver(&bflb_uart_driver);
+	if (ret)
+		return ret;
+
+	ret = platform_driver_register(&bflb_uart_platform_driver);
+	if (ret)
+		uart_unregister_driver(&bflb_uart_driver);
+
+	return ret;
+}
+
+static void __exit bflb_uart_exit(void)
+{
+	platform_driver_unregister(&bflb_uart_platform_driver);
+	uart_unregister_driver(&bflb_uart_driver);
+}
+
+module_init(bflb_uart_init);
+module_exit(bflb_uart_exit);
+
+MODULE_DESCRIPTION("Bouffalolab UART driver");
+MODULE_AUTHOR("Jisheng Zhang <jszhang@kernel.org>");
+MODULE_LICENSE("GPL");
diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h
index 3ba34d8378bd..dabbb5ea2857 100644
--- a/include/uapi/linux/serial_core.h
+++ b/include/uapi/linux/serial_core.h
@@ -276,4 +276,7 @@
 /* Sunplus UART */
 #define PORT_SUNPLUS	123
 
+/* Bouffalolab UART */
+#define PORT_BFLB	124
+
 #endif /* _UAPILINUX_SERIAL_CORE_H */
-- 
2.38.1

[PATCH v2 3/9] riscv: add the Bouffalolab SoC family Kconfig option

[Jisheng Zhang]

The Bouffalolab bl808 SoC contains three riscv CPUs, namely M0, D0 and
LP. The D0 is 64bit RISC-V GC compatible, so can run linux.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/Kconfig.socs | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 69774bb362d6..90256f44ed4a 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -1,5 +1,11 @@
 menu "SoC selection"
 
+config SOC_BOUFFALOLAB
+	bool "Bouffalolab SoCs"
+	select SIFIVE_PLIC
+	help
+	  This enables support for Bouffalolab SoC platforms.
+
 config SOC_MICROCHIP_POLARFIRE
 	bool "Microchip PolarFire SoCs"
 	select MCHP_CLK_MPFS
-- 
2.38.1

[PATCH v2 4/9] dt-bindings: vendor-prefixes: add bouffalolab

[Jisheng Zhang]

In the following commits, we will support bl808 SoC which is from
Bouffalo Lab Technology (Nanjing) Co., Ltd.

Add bouffalolab vendor prefix binding.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 6e323a380294..81618f1dc01b 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -194,6 +194,8 @@ patternProperties:
     description: BOE Technology Group Co., Ltd.
   "^bosch,.*":
     description: Bosch Sensortec GmbH
+  "^bouffalolab,.*":
+    description: Bouffalo Lab Technology (Nanjing) Co., Ltd.
   "^boundary,.*":
     description: Boundary Devices Inc.
   "^broadmobi,.*":
-- 
2.38.1

[PATCH v2 5/9] dt-bindings: riscv: Add bouffalolab bl808 board compatibles

[Jisheng Zhang]

Several SoMs and boards are available that feature the Bouffalolab
bl808 SoC. Document the compatible strings.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
 .../bindings/riscv/bouffalolab.yaml           | 34 +++++++++++++++++++
 1 file changed, 34 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/bouffalolab.yaml

diff --git a/Documentation/devicetree/bindings/riscv/bouffalolab.yaml b/Documentation/devicetree/bindings/riscv/bouffalolab.yaml
new file mode 100644
index 000000000000..91ca9dbdc798
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/bouffalolab.yaml
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/bouffalolab.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bouffalo Lab Technology SoC-based boards
+
+maintainers:
+  - Jisheng Zhang <jszhang@kernel.org>
+
+description:
+  Bouffalo Lab Technology SoC-based boards
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - description: Sipeed M1s SoM:
+        items:
+          - const: sipeed,m1s
+          - const: bouffalolab,bl808
+
+      - description: Carrier boards for the Sipeed M1s SoM:
+        items:
+          - enum:
+              - sipeed,m1s-dock
+          - const: sipeed,m1s
+          - const: bouffalolab,bl808
+
+additionalProperties: true
+
+...
-- 
2.38.1

[PATCH v2 6/9] riscv: dts: bouffalolab: add the bl808 SoC base device tree

[Jisheng Zhang]

Add a baisc dtsi for the bouffalolab bl808 SoC.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
 arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 ++++++++++++++++++++++
 1 file changed, 74 insertions(+)
 create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi

diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
new file mode 100644
index 000000000000..f4b170ccc32e
--- /dev/null
+++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	compatible = "bouffalolab,bl808";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		timebase-frequency = <1000000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "thead,c906", "riscv";
+			device_type = "cpu";
+			reg = <0>;
+			d-cache-block-size = <64>;
+			d-cache-sets = <256>;
+			d-cache-size = <32768>;
+			i-cache-block-size = <64>;
+			i-cache-sets = <128>;
+			i-cache-size = <32768>;
+			mmu-type = "riscv,sv39";
+			riscv,isa = "rv64imafdc";
+
+			cpu0_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+			};
+		};
+	};
+
+	xtal: xtal-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		ranges;
+		interrupt-parent = <&plic>;
+		dma-noncoherent;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		uart0: serial@30002000 {
+			compatible = "bouffalolab,bl808-uart";
+			reg = <0x30002000 0x1000>;
+			interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&xtal>;
+			status = "disabled";
+		};
+
+		plic: interrupt-controller@e0000000 {
+			compatible = "thead,c900-plic";
+			reg = <0xe0000000 0x4000000>;
+			interrupts-extended = <&cpu0_intc 0xffffffff>,
+					      <&cpu0_intc 9>;
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			riscv,ndev = <64>;
+		};
+	};
+};
-- 
2.38.1

[PATCH v2 7/9] riscv: dts: bouffalolab: add Sipeed M1s SoM and Dock devicetree

[Jisheng Zhang]

Sipeed manufactures a M1s system-on-module and dock board, add basic
support for them.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
 arch/riscv/boot/dts/Makefile                  |  1 +
 arch/riscv/boot/dts/bouffalolab/Makefile      |  2 ++
 .../dts/bouffalolab/bl808-sipeed-m1s-dock.dts | 25 +++++++++++++++++++
 .../dts/bouffalolab/bl808-sipeed-m1s.dtsi     | 21 ++++++++++++++++
 4 files changed, 49 insertions(+)
 create mode 100644 arch/riscv/boot/dts/bouffalolab/Makefile
 create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s-dock.dts
 create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dtsi

diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index ff174996cdfd..b525467152b2 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -1,4 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0
+subdir-y += bouffalolab
 subdir-y += sifive
 subdir-y += starfive
 subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
diff --git a/arch/riscv/boot/dts/bouffalolab/Makefile b/arch/riscv/boot/dts/bouffalolab/Makefile
new file mode 100644
index 000000000000..5419964e892d
--- /dev/null
+++ b/arch/riscv/boot/dts/bouffalolab/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_SOC_BOUFFALOLAB) += bl808-sipeed-m1s-dock.dtb
diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s-dock.dts b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s-dock.dts
new file mode 100644
index 000000000000..c6b4894a7b88
--- /dev/null
+++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s-dock.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
+ */
+
+/dts-v1/;
+
+#include "bl808-sipeed-m1s.dtsi"
+
+/ {
+	model = "Sipeed M1s Dock";
+	compatible = "sipeed,m1s-dock", "sipeed,m1s", "bouffalolab,bl808";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:2000000n8";
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dtsi
new file mode 100644
index 000000000000..5026de768534
--- /dev/null
+++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
+ */
+
+/dts-v1/;
+
+#include "bl808.dtsi"
+
+/ {
+	compatible = "sipeed,m1s", "bouffalolab,bl808";
+
+	memory@50000000 {
+		device_type = "memory";
+		reg = <0x50000000 0x04000000>;
+	};
+};
+
+&xtal {
+	clock-frequency = <40000000>;
+};
-- 
2.38.1

[PATCH v2 8/9] MAINTAINERS: riscv: add entry for Bouffalolab SoC

[Jisheng Zhang]

Add Jisheng Zhang as Bouffalolab SoC maintainer.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
 MAINTAINERS | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 00ff4a2949b8..a6b04249853c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17729,6 +17729,15 @@ F:	arch/riscv/
 N:	riscv
 K:	riscv
 
+RISC-V BOUFFALOLAB SOC SUPPORT
+M:	Jisheng Zhang <jszhang@kernel.org>
+L:	linux-riscv@lists.infradead.org
+S:	Maintained
+F:	Documentation/devicetree/bindings/riscv/bouffalolab.yaml
+F:	Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml
+F:	arch/riscv/boot/dts/bouffalolab/
+F:	drivers/tty/serial/bflb_uart.c
+
 RISC-V MICROCHIP FPGA SUPPORT
 M:	Conor Dooley <conor.dooley@microchip.com>
 M:	Daire McNamara <daire.mcnamara@microchip.com>
-- 
2.38.1

[PATCH v2 9/9] riscv: defconfig: enable BOUFFALOLAB SoC

[Jisheng Zhang]

Enable BOUFFALOLAB soc config in defconfig to allow the default
upstream kernel to boot on Sipeed M1s Dock board.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
 arch/riscv/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 05fd5fcf24f9..27b3d59c7d90 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -25,6 +25,7 @@ CONFIG_BLK_DEV_INITRD=y
 CONFIG_EXPERT=y
 # CONFIG_SYSFS_SYSCALL is not set
 CONFIG_PROFILING=y
+CONFIG_SOC_BOUFFALOLAB=y
 CONFIG_SOC_MICROCHIP_POLARFIRE=y
 CONFIG_SOC_SIFIVE=y
 CONFIG_SOC_STARFIVE=y
-- 
2.38.1

Re: [PATCH v2 5/9] dt-bindings: riscv: Add bouffalolab bl808 board compatibles

[Rob Herring]

On Sun, 27 Nov 2022 21:24:44 +0800, Jisheng Zhang wrote:
> Several SoMs and boards are available that feature the Bouffalolab
> bl808 SoC. Document the compatible strings.
> 
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
>  .../bindings/riscv/bouffalolab.yaml           | 34 +++++++++++++++++++
>  1 file changed, 34 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/riscv/bouffalolab.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:
./Documentation/devicetree/bindings/riscv/bouffalolab.yaml:20:36: [error] syntax error: mapping values are not allowed here (syntax)

dtschema/dtc warnings/errors:
make[1]: *** Deleting file 'Documentation/devicetree/bindings/riscv/bouffalolab.example.dts'
Documentation/devicetree/bindings/riscv/bouffalolab.yaml:20:36: mapping values are not allowed in this context
make[1]: *** [Documentation/devicetree/bindings/Makefile:26: Documentation/devicetree/bindings/riscv/bouffalolab.example.dts] Error 1
make[1]: *** Waiting for unfinished jobs....
./Documentation/devicetree/bindings/riscv/bouffalolab.yaml:20:36: mapping values are not allowed in this context
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/riscv/bouffalolab.yaml: ignoring, error parsing file
make: *** [Makefile:1492: dt_binding_check] Error 2

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20221127132448.4034-6-jszhang@kernel.org

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command.

Re: [PATCH v2 6/9] riscv: dts: bouffalolab: add the bl808 SoC base device tree

[Conor Dooley]

+CC Icenowy

On Sun, Nov 27, 2022 at 09:24:45PM +0800, Jisheng Zhang wrote:
> Add a baisc dtsi for the bouffalolab bl808 SoC.
> 
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
>  arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 ++++++++++++++++++++++
>  1 file changed, 74 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> 
> diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> new file mode 100644
> index 000000000000..f4b170ccc32e
> --- /dev/null
> +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> @@ -0,0 +1,74 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +/*
> + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> +	compatible = "bouffalolab,bl808";
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	cpus {
> +		timebase-frequency = <1000000>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu@0 {
> +			compatible = "thead,c906", "riscv";
> +			device_type = "cpu";
> +			reg = <0>;
> +			d-cache-block-size = <64>;
> +			d-cache-sets = <256>;
> +			d-cache-size = <32768>;
> +			i-cache-block-size = <64>;
> +			i-cache-sets = <128>;
> +			i-cache-size = <32768>;
> +			mmu-type = "riscv,sv39";
> +			riscv,isa = "rv64imafdc";
> +
> +			cpu0_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#address-cells = <0>;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +	};
> +
> +	xtal: xtal-clk {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		/* This value must be overridden by the board */
> +		clock-frequency = <0>;
> +	};
> +
> +	soc {
> +		compatible = "simple-bus";
> +		ranges;
> +		interrupt-parent = <&plic>;
> +		dma-noncoherent;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +
> +		uart0: serial@30002000 {
> +			compatible = "bouffalolab,bl808-uart";
> +			reg = <0x30002000 0x1000>;
> +			interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&xtal>;
> +			status = "disabled";
> +		};
> +
> +		plic: interrupt-controller@e0000000 {
> +			compatible = "thead,c900-plic";

Hmm, @Icenowy - should this use your new open-c906-plic compatible from
20221121041757.418645-4-uwu@icenowy.me ?

As is, dtbs_check gives a:
bl808-sipeed-m1s-dock.dtb: interrupt-controller@e0000000: compatible: 'oneOf' conditional failed, one must be fixed:
        ['thead,c900-plic'] is too short

> +			reg = <0xe0000000 0x4000000>;
> +			interrupts-extended = <&cpu0_intc 0xffffffff>,
> +					      <&cpu0_intc 9>;
> +			interrupt-controller;
> +			#address-cells = <0>;
> +			#interrupt-cells = <2>;
> +			riscv,ndev = <64>;
> +		};
> +	};
> +};
> -- 
> 2.38.1
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v2 4/9] dt-bindings: vendor-prefixes: add bouffalolab

[Conor Dooley]

On Sun, Nov 27, 2022 at 09:24:43PM +0800, Jisheng Zhang wrote:
> In the following commits, we will support bl808 SoC which is from
> Bouffalo Lab Technology (Nanjing) Co., Ltd.
> 
> Add bouffalolab vendor prefix binding.
> 

Perhaps add
Link: https://en.bouffalolab.com/
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
>  Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> index 6e323a380294..81618f1dc01b 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> @@ -194,6 +194,8 @@ patternProperties:
>      description: BOE Technology Group Co., Ltd.
>    "^bosch,.*":
>      description: Bosch Sensortec GmbH
> +  "^bouffalolab,.*":
> +    description: Bouffalo Lab Technology (Nanjing) Co., Ltd.
>    "^boundary,.*":
>      description: Boundary Devices Inc.
>    "^broadmobi,.*":
> -- 
> 2.38.1
> 

Re: [PATCH v2 5/9] dt-bindings: riscv: Add bouffalolab bl808 board compatibles

[Conor Dooley]

On Sun, Nov 27, 2022 at 09:24:44PM +0800, Jisheng Zhang wrote:
> Several SoMs and boards are available that feature the Bouffalolab
> bl808 SoC. Document the compatible strings.
> 
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
>  .../bindings/riscv/bouffalolab.yaml           | 34 +++++++++++++++++++
>  1 file changed, 34 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/riscv/bouffalolab.yaml
> 
> diff --git a/Documentation/devicetree/bindings/riscv/bouffalolab.yaml b/Documentation/devicetree/bindings/riscv/bouffalolab.yaml
> new file mode 100644
> index 000000000000..91ca9dbdc798
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/riscv/bouffalolab.yaml
> @@ -0,0 +1,34 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/riscv/bouffalolab.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Bouffalo Lab Technology SoC-based boards
> +
> +maintainers:
> +  - Jisheng Zhang <jszhang@kernel.org>
> +
> +description:
> +  Bouffalo Lab Technology SoC-based boards
> +
> +properties:
> +  $nodename:
> +    const: '/'
> +  compatible:
> +    oneOf:
> +      - description: Sipeed M1s SoM:
                                      ^
Drop these :s in the descriptions to placate Rob's bot :)

> +        items:
> +          - const: sipeed,m1s
> +          - const: bouffalolab,bl808
> +
> +      - description: Carrier boards for the Sipeed M1s SoM:
> +        items:
> +          - enum:
> +              - sipeed,m1s-dock

Do we need the enum when there's only one? I assume you're future
proofing against adding more carriers?

Otherwise than those two bits:
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

> +          - const: sipeed,m1s
> +          - const: bouffalolab,bl808
> +
> +additionalProperties: true
> +
> +...
> -- 
> 2.38.1
> 

Re: [PATCH v2 7/9] riscv: dts: bouffalolab: add Sipeed M1s SoM and Dock devicetree

[Conor Dooley]

On Sun, Nov 27, 2022 at 09:24:46PM +0800, Jisheng Zhang wrote:
> Sipeed manufactures a M1s system-on-module and dock board, add basic
> support for them.
> 
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>

Other than the plic compatibe in 5/9 needing a fix one way or another,
the dts looks fine so
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.

> ---
>  arch/riscv/boot/dts/Makefile                  |  1 +
>  arch/riscv/boot/dts/bouffalolab/Makefile      |  2 ++
>  .../dts/bouffalolab/bl808-sipeed-m1s-dock.dts | 25 +++++++++++++++++++
>  .../dts/bouffalolab/bl808-sipeed-m1s.dtsi     | 21 ++++++++++++++++
>  4 files changed, 49 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/bouffalolab/Makefile
>  create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s-dock.dts
>  create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dtsi
> 
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index ff174996cdfd..b525467152b2 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -1,4 +1,5 @@
>  # SPDX-License-Identifier: GPL-2.0
> +subdir-y += bouffalolab
>  subdir-y += sifive
>  subdir-y += starfive
>  subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> diff --git a/arch/riscv/boot/dts/bouffalolab/Makefile b/arch/riscv/boot/dts/bouffalolab/Makefile
> new file mode 100644
> index 000000000000..5419964e892d
> --- /dev/null
> +++ b/arch/riscv/boot/dts/bouffalolab/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_SOC_BOUFFALOLAB) += bl808-sipeed-m1s-dock.dtb
> diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s-dock.dts b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s-dock.dts
> new file mode 100644
> index 000000000000..c6b4894a7b88
> --- /dev/null
> +++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s-dock.dts
> @@ -0,0 +1,25 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +/*
> + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
> + */
> +
> +/dts-v1/;
> +
> +#include "bl808-sipeed-m1s.dtsi"
> +
> +/ {
> +	model = "Sipeed M1s Dock";
> +	compatible = "sipeed,m1s-dock", "sipeed,m1s", "bouffalolab,bl808";
> +
> +	aliases {
> +		serial0 = &uart0;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:2000000n8";
> +	};
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dtsi
> new file mode 100644
> index 000000000000..5026de768534
> --- /dev/null
> +++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dtsi
> @@ -0,0 +1,21 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +/*
> + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
> + */
> +
> +/dts-v1/;
> +
> +#include "bl808.dtsi"
> +
> +/ {
> +	compatible = "sipeed,m1s", "bouffalolab,bl808";
> +
> +	memory@50000000 {
> +		device_type = "memory";
> +		reg = <0x50000000 0x04000000>;
> +	};
> +};
> +
> +&xtal {
> +	clock-frequency = <40000000>;
> +};
> -- 
> 2.38.1
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v2 8/9] MAINTAINERS: riscv: add entry for Bouffalolab SoC

[Conor Dooley]

Hey Jisheng,

On Sun, Nov 27, 2022 at 09:24:47PM +0800, Jisheng Zhang wrote:
> Add Jisheng Zhang as Bouffalolab SoC maintainer.
> 
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
>  MAINTAINERS | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 00ff4a2949b8..a6b04249853c 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -17729,6 +17729,15 @@ F:	arch/riscv/
>  N:	riscv
>  K:	riscv
>  
> +RISC-V BOUFFALOLAB SOC SUPPORT
> +M:	Jisheng Zhang <jszhang@kernel.org>
> +L:	linux-riscv@lists.infradead.org
> +S:	Maintained
> +F:	Documentation/devicetree/bindings/riscv/bouffalolab.yaml
> +F:	Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml
> +F:	arch/riscv/boot/dts/bouffalolab/
> +F:	drivers/tty/serial/bflb_uart.c

I think I asked last time but I didn't see an answer on lore or my
mailbox - if you intend sending Arnd PRs for this stuff, please add a
git tree here. Otherwise, LMK and I'll bundle it with the other "misc
riscv devicetree" stuff.

Thanks,
Conor.

>  RISC-V MICROCHIP FPGA SUPPORT
>  M:	Conor Dooley <conor.dooley@microchip.com>
>  M:	Daire McNamara <daire.mcnamara@microchip.com>
> -- 
> 2.38.1
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v2 9/9] riscv: defconfig: enable BOUFFALOLAB SoC

[Conor Dooley]

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Re: [PATCH v2 8/9] MAINTAINERS: riscv: add entry for Bouffalolab SoC

[Conor Dooley]

On Sun, Nov 27, 2022 at 05:35:48PM +0000, Conor Dooley wrote:
> Hey Jisheng,
> 
> On Sun, Nov 27, 2022 at 09:24:47PM +0800, Jisheng Zhang wrote:
> > Add Jisheng Zhang as Bouffalolab SoC maintainer.
> > 
> > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > ---
> >  MAINTAINERS | 9 +++++++++
> >  1 file changed, 9 insertions(+)
> > 
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 00ff4a2949b8..a6b04249853c 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -17729,6 +17729,15 @@ F:	arch/riscv/
> >  N:	riscv
> >  K:	riscv
> >  
> > +RISC-V BOUFFALOLAB SOC SUPPORT
> > +M:	Jisheng Zhang <jszhang@kernel.org>
> > +L:	linux-riscv@lists.infradead.org
> > +S:	Maintained
> > +F:	Documentation/devicetree/bindings/riscv/bouffalolab.yaml
> > +F:	Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml
> > +F:	arch/riscv/boot/dts/bouffalolab/
> > +F:	drivers/tty/serial/bflb_uart.c
> 
> I think I asked last time but I didn't see an answer on lore or my
> mailbox - if you intend sending Arnd PRs for this stuff, please add a
> git tree here. Otherwise, LMK and I'll bundle it with the other "misc
> riscv devicetree" stuff.

I forgot:
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

> >  RISC-V MICROCHIP FPGA SUPPORT
> >  M:	Conor Dooley <conor.dooley@microchip.com>
> >  M:	Daire McNamara <daire.mcnamara@microchip.com>
> > -- 
> > 2.38.1
> > 
> > 
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v2 2/9] serial: bflb_uart: add Bouffalolab UART Driver

[Jiri Slaby]

On 27. 11. 22, 14:24, Jisheng Zhang wrote:
> +static void bflb_uart_tx_chars(struct uart_port *port)

Again:

Are you unable to use the TX helper? If so:
* why?
* use uart_advance_xmit() at least.

> +{
> +	struct circ_buf *xmit = &port->state->xmit;
> +	unsigned int count;
> +
> +	if (port->x_char) {
> +		/* Send special char - probably flow control */
> +		wrl(port, UART_FIFO_WDATA, port->x_char);
> +		port->x_char = 0;
> +		port->icount.tx++;
> +		return;
> +	}
> +
> +	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
> +		bflb_uart_stop_tx(port);
> +		return;
> +	}
> +
> +	count = BFLB_UART_TX_FIFO_TH;
> +	do {
> +		wrl(port, UART_FIFO_WDATA, xmit->buf[xmit->tail]);
> +		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
> +		port->icount.tx++;
> +		if (uart_circ_empty(xmit))
> +			break;
> +	} while (--count > 0);
> +
> +	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
> +		uart_write_wakeup(port);
> +
> +	if (uart_circ_empty(xmit))
> +		bflb_uart_stop_tx(port);
> +}

-- 
js
suse labs

Re: [PATCH v2 6/9] riscv: dts: bouffalolab: add the bl808 SoC base device tree

[Icenowy Zheng]

在 2022-11-27星期日的 17:21 +0000，Conor Dooley写道：
> +CC Icenowy
> 
> On Sun, Nov 27, 2022 at 09:24:45PM +0800, Jisheng Zhang wrote:
> > Add a baisc dtsi for the bouffalolab bl808 SoC.
> > 
> > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > ---
> >  arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74
> > ++++++++++++++++++++++
> >  1 file changed, 74 insertions(+)
> >  create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> > 
> > diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> > b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> > new file mode 100644
> > index 000000000000..f4b170ccc32e
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> > @@ -0,0 +1,74 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> > +/*
> > + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +
> > +/ {
> > +       compatible = "bouffalolab,bl808";
> > +       #address-cells = <1>;
> > +       #size-cells = <1>;
> > +
> > +       cpus {
> > +               timebase-frequency = <1000000>;
> > +               #address-cells = <1>;
> > +               #size-cells = <0>;
> > +
> > +               cpu0: cpu@0 {
> > +                       compatible = "thead,c906", "riscv";
> > +                       device_type = "cpu";
> > +                       reg = <0>;
> > +                       d-cache-block-size = <64>;
> > +                       d-cache-sets = <256>;
> > +                       d-cache-size = <32768>;
> > +                       i-cache-block-size = <64>;
> > +                       i-cache-sets = <128>;
> > +                       i-cache-size = <32768>;
> > +                       mmu-type = "riscv,sv39";
> > +                       riscv,isa = "rv64imafdc";
> > +
> > +                       cpu0_intc: interrupt-controller {
> > +                               compatible = "riscv,cpu-intc";
> > +                               interrupt-controller;
> > +                               #address-cells = <0>;
> > +                               #interrupt-cells = <1>;
> > +                       };
> > +               };
> > +       };
> > +
> > +       xtal: xtal-clk {
> > +               compatible = "fixed-clock";
> > +               #clock-cells = <0>;
> > +               /* This value must be overridden by the board */
> > +               clock-frequency = <0>;
> > +       };
> > +
> > +       soc {
> > +               compatible = "simple-bus";
> > +               ranges;
> > +               interrupt-parent = <&plic>;
> > +               dma-noncoherent;
> > +               #address-cells = <1>;
> > +               #size-cells = <1>;
> > +
> > +               uart0: serial@30002000 {
> > +                       compatible = "bouffalolab,bl808-uart";
> > +                       reg = <0x30002000 0x1000>;
> > +                       interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&xtal>;
> > +                       status = "disabled";
> > +               };
> > +
> > +               plic: interrupt-controller@e0000000 {
> > +                       compatible = "thead,c900-plic";
> 
> Hmm, @Icenowy - should this use your new open-c906-plic compatible
> from
> 20221121041757.418645-4-uwu@icenowy.me ?

I am against using openc906-plic.

Maybe I will add "thead,c906-plic", "thead,c900-plic" as an valid
compatible, as there seems to be few options related to PLIC/CLINT for
C906/C910 (at least as the open document of them say).

> 
> As is, dtbs_check gives a:
> bl808-sipeed-m1s-dock.dtb: interrupt-controller@e0000000: compatible:
> 'oneOf' conditional failed, one must be fixed:
>         ['thead,c900-plic'] is too short
> 
> > +                       reg = <0xe0000000 0x4000000>;
> > +                       interrupts-extended = <&cpu0_intc
> > 0xffffffff>,
> > +                                             <&cpu0_intc 9>;
> > +                       interrupt-controller;
> > +                       #address-cells = <0>;
> > +                       #interrupt-cells = <2>;
> > +                       riscv,ndev = <64>;
> > +               };
> > +       };
> > +};
> > -- 
> > 2.38.1
> > 
> > 
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v2 2/9] serial: bflb_uart: add Bouffalolab UART Driver

[Jisheng Zhang]

On Mon, Nov 28, 2022 at 07:10:41AM +0100, Jiri Slaby wrote:
> On 27. 11. 22, 14:24, Jisheng Zhang wrote:
> > +static void bflb_uart_tx_chars(struct uart_port *port)
> 
> Again:
> 
> Are you unable to use the TX helper? If so:

You know serial subsystem better than me, may I ask for more
details? For example,
Besides uart_xmit_advance(), do you expect other TX helpers? If yes,
can you please list them?

> * why?
> * use uart_advance_xmit() at least.

Do you mean uart_xmit_advance()? in the do while loop below?

I'm not sure I understand the meaning, correct me If I misunderstand
something.

thanks
> 
> > +{
> > +	struct circ_buf *xmit = &port->state->xmit;
> > +	unsigned int count;
> > +
> > +	if (port->x_char) {
> > +		/* Send special char - probably flow control */
> > +		wrl(port, UART_FIFO_WDATA, port->x_char);
> > +		port->x_char = 0;
> > +		port->icount.tx++;
> > +		return;
> > +	}
> > +
> > +	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
> > +		bflb_uart_stop_tx(port);
> > +		return;
> > +	}
> > +
> > +	count = BFLB_UART_TX_FIFO_TH;
> > +	do {
> > +		wrl(port, UART_FIFO_WDATA, xmit->buf[xmit->tail]);
> > +		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
> > +		port->icount.tx++;
> > +		if (uart_circ_empty(xmit))
> > +			break;
> > +	} while (--count > 0);
> > +
> > +	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
> > +		uart_write_wakeup(port);
> > +
> > +	if (uart_circ_empty(xmit))
> > +		bflb_uart_stop_tx(port);
> > +}
> 
> -- 
> js
> suse labs
> 

Re: [PATCH v2 8/9] MAINTAINERS: riscv: add entry for Bouffalolab SoC

[Jisheng Zhang]

On Sun, Nov 27, 2022 at 05:36:53PM +0000, Conor Dooley wrote:
> On Sun, Nov 27, 2022 at 05:35:48PM +0000, Conor Dooley wrote:
> > Hey Jisheng,
> > 
> > On Sun, Nov 27, 2022 at 09:24:47PM +0800, Jisheng Zhang wrote:
> > > Add Jisheng Zhang as Bouffalolab SoC maintainer.
> > > 
> > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > > ---
> > >  MAINTAINERS | 9 +++++++++
> > >  1 file changed, 9 insertions(+)
> > > 
> > > diff --git a/MAINTAINERS b/MAINTAINERS
> > > index 00ff4a2949b8..a6b04249853c 100644
> > > --- a/MAINTAINERS
> > > +++ b/MAINTAINERS
> > > @@ -17729,6 +17729,15 @@ F:	arch/riscv/
> > >  N:	riscv
> > >  K:	riscv
> > >  
> > > +RISC-V BOUFFALOLAB SOC SUPPORT
> > > +M:	Jisheng Zhang <jszhang@kernel.org>
> > > +L:	linux-riscv@lists.infradead.org
> > > +S:	Maintained
> > > +F:	Documentation/devicetree/bindings/riscv/bouffalolab.yaml
> > > +F:	Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml
> > > +F:	arch/riscv/boot/dts/bouffalolab/
> > > +F:	drivers/tty/serial/bflb_uart.c
> > 
> > I think I asked last time but I didn't see an answer on lore or my
> > mailbox - if you intend sending Arnd PRs for this stuff, please add a

Per my past experience of synaptics/mrvl arm SoCs, I usually sent PRs to Arnd
if there are two or more commits/patches; If there's only one patch, I
asked Arnd for picking it up directly. So in bouffalolab SoC case, I
want to do similar, but with one difference -- if there's only one
patch, may I ask you for picking it up directly?

> > git tree here. Otherwise, LMK and I'll bundle it with the other "misc

Hmm, is "git tree" necessary?

> > riscv devicetree" stuff.
> 
> I forgot:
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> 
> > >  RISC-V MICROCHIP FPGA SUPPORT
> > >  M:	Conor Dooley <conor.dooley@microchip.com>
> > >  M:	Daire McNamara <daire.mcnamara@microchip.com>
> > > -- 
> > > 2.38.1
> > > 
> > > 
> > > _______________________________________________
> > > linux-riscv mailing list
> > > linux-riscv@lists.infradead.org
> > > http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v2 8/9] MAINTAINERS: riscv: add entry for Bouffalolab SoC

[Jisheng Zhang]

On Mon, Nov 28, 2022 at 10:30:15PM +0800, Jisheng Zhang wrote:
> On Sun, Nov 27, 2022 at 05:36:53PM +0000, Conor Dooley wrote:
> > On Sun, Nov 27, 2022 at 05:35:48PM +0000, Conor Dooley wrote:
> > > Hey Jisheng,
> > > 
> > > On Sun, Nov 27, 2022 at 09:24:47PM +0800, Jisheng Zhang wrote:
> > > > Add Jisheng Zhang as Bouffalolab SoC maintainer.
> > > > 
> > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > > > ---
> > > >  MAINTAINERS | 9 +++++++++
> > > >  1 file changed, 9 insertions(+)
> > > > 
> > > > diff --git a/MAINTAINERS b/MAINTAINERS
> > > > index 00ff4a2949b8..a6b04249853c 100644
> > > > --- a/MAINTAINERS
> > > > +++ b/MAINTAINERS
> > > > @@ -17729,6 +17729,15 @@ F:	arch/riscv/
> > > >  N:	riscv
> > > >  K:	riscv
> > > >  
> > > > +RISC-V BOUFFALOLAB SOC SUPPORT
> > > > +M:	Jisheng Zhang <jszhang@kernel.org>
> > > > +L:	linux-riscv@lists.infradead.org
> > > > +S:	Maintained
> > > > +F:	Documentation/devicetree/bindings/riscv/bouffalolab.yaml
> > > > +F:	Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml
> > > > +F:	arch/riscv/boot/dts/bouffalolab/
> > > > +F:	drivers/tty/serial/bflb_uart.c
> > > 
> > > I think I asked last time but I didn't see an answer on lore or my
> > > mailbox - if you intend sending Arnd PRs for this stuff, please add a
> 
> Per my past experience of synaptics/mrvl arm SoCs, I usually sent PRs to Arnd
> if there are two or more commits/patches; If there's only one patch, I
> asked Arnd for picking it up directly. So in bouffalolab SoC case, I
> want to do similar, but with one difference -- if there's only one
> patch, may I ask you for picking it up directly?

That's to say: If there are two or more commits/patches, I will send
Arnd PRs; If there's only one commit/patch, I will ask your help to
picking it up directly.

> 
> > > git tree here. Otherwise, LMK and I'll bundle it with the other "misc
> 
> Hmm, is "git tree" necessary?
> 
> > > riscv devicetree" stuff.
> > 
> > I forgot:
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > 
> > > >  RISC-V MICROCHIP FPGA SUPPORT
> > > >  M:	Conor Dooley <conor.dooley@microchip.com>
> > > >  M:	Daire McNamara <daire.mcnamara@microchip.com>
> > > > -- 
> > > > 2.38.1
> > > > 
> > > > 
> > > > _______________________________________________
> > > > linux-riscv mailing list
> > > > linux-riscv@lists.infradead.org
> > > > http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v2 8/9] MAINTAINERS: riscv: add entry for Bouffalolab SoC

[Conor Dooley]

Hey Jisheng,

On Mon, Nov 28, 2022 at 10:30:08PM +0800, Jisheng Zhang wrote:

> Per my past experience of synaptics/mrvl arm SoCs, I usually sent PRs to Arnd
> if there are two or more commits/patches; If there's only one patch, I
> asked Arnd for picking it up directly. So in bouffalolab SoC case, I
> want to do similar, but with one difference -- if there's only one
> patch, may I ask you for picking it up directly?

Works for me :) Unless I hear otherwise on a given patch, I'll assume
you've got it taken care of.

> > > git tree here. Otherwise, LMK and I'll bundle it with the other "misc
> 
> Hmm, is "git tree" necessary?

If you have one that you're sending PRs from, it's nice to know
what/where someone that may have a patch for your stuff can base
their changes on. You don't need to obviously.

Thanks!
Conor.

Re: [PATCH v2 6/9] riscv: dts: bouffalolab: add the bl808 SoC base device tree

[Conor Dooley]

On Mon, Nov 28, 2022 at 05:52:51PM +0800, Icenowy Zheng wrote:
> 在 2022-11-27星期日的 17:21 +0000，Conor Dooley写道：
> > +CC Icenowy
> > 
> > On Sun, Nov 27, 2022 at 09:24:45PM +0800, Jisheng Zhang wrote:
> > > Add a baisc dtsi for the bouffalolab bl808 SoC.
> > > 
> > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > > ---
> > >  arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74

> > > +               plic: interrupt-controller@e0000000 {
> > > +                       compatible = "thead,c900-plic";
> > 
> > Hmm, @Icenowy - should this use your new open-c906-plic compatible
> > from
> > 20221121041757.418645-4-uwu@icenowy.me ?
> 
> I am against using openc906-plic.
> 
> Maybe I will add "thead,c906-plic", "thead,c900-plic" as an valid
> compatible, as there seems to be few options related to PLIC/CLINT for
> C906/C910 (at least as the open document of them say).

You two know this a lot better than I do, I'll leave it up to you two to
sort out :) Either way, we need something changed here to satisfy the
bindings.

> > As is, dtbs_check gives a:
> > bl808-sipeed-m1s-dock.dtb: interrupt-controller@e0000000: compatible:
> > 'oneOf' conditional failed, one must be fixed:
> >         ['thead,c900-plic'] is too short
> > 
> > > +                       reg = <0xe0000000 0x4000000>;
> > > +                       interrupts-extended = <&cpu0_intc
> > > 0xffffffff>,
> > > +                                             <&cpu0_intc 9>;
> > > +                       interrupt-controller;
> > > +                       #address-cells = <0>;
> > > +                       #interrupt-cells = <2>;
> > > +                       riscv,ndev = <64>;
> > > +               };
> > > +       };
> > > +};

Re: [PATCH v2 2/9] serial: bflb_uart: add Bouffalolab UART Driver

[Ilpo Järvinen]

On Mon, 28 Nov 2022, Jisheng Zhang wrote:

> On Mon, Nov 28, 2022 at 07:10:41AM +0100, Jiri Slaby wrote:
> > On 27. 11. 22, 14:24, Jisheng Zhang wrote:
> > > +static void bflb_uart_tx_chars(struct uart_port *port)
> > 
> > Again:
> > 
> > Are you unable to use the TX helper? If so:
> 
> You know serial subsystem better than me, may I ask for more
> details? For example,
> Besides uart_xmit_advance(), do you expect other TX helpers? If yes,
> can you please list them?

Please take on look on commit 8275b48b278096edc1e3ea5aa9cf946a10022f79.
The changes following that commit convert some drivers to use the tx 
helper so you can look into them to see examples.

> > * why?
> > * use uart_advance_xmit() at least.
> 
> Do you mean uart_xmit_advance()? in the do while loop below?

Yes, Jiri had the name wrong. But your code looked like it could use 
the tx helper instead.

-- 
 i.

Re: [PATCH v2 2/9] serial: bflb_uart: add Bouffalolab UART Driver

[Jisheng Zhang]

On Mon, Nov 28, 2022 at 06:01:28PM +0200, Ilpo Järvinen wrote:
> On Mon, 28 Nov 2022, Jisheng Zhang wrote:
> 
> > On Mon, Nov 28, 2022 at 07:10:41AM +0100, Jiri Slaby wrote:
> > > On 27. 11. 22, 14:24, Jisheng Zhang wrote:
> > > > +static void bflb_uart_tx_chars(struct uart_port *port)
> > > 
> > > Again:
> > > 
> > > Are you unable to use the TX helper? If so:
> > 
> > You know serial subsystem better than me, may I ask for more
> > details? For example,
> > Besides uart_xmit_advance(), do you expect other TX helpers? If yes,
> > can you please list them?
> 
> Please take on look on commit 8275b48b278096edc1e3ea5aa9cf946a10022f79.
> The changes following that commit convert some drivers to use the tx 
> helper so you can look into them to see examples.

Thanks a lot for the hint. Will those tx helpers(uart_port_tx,
uart_port_tx_limited etc.) be in v6.2-rc1? Or I need to patch
based on Jiri's devel branch? Aha, Jiri says "at least uart_xmit_advance

> 
> > > * why?
> > > * use uart_advance_xmit() at least.
> > 
> > Do you mean uart_xmit_advance()? in the do while loop below?
> 
> Yes, Jiri had the name wrong. But your code looked like it could use 
> the tx helper instead.

Re: [PATCH v2 2/9] serial: bflb_uart: add Bouffalolab UART Driver

[Jiri Slaby]

On 29. 11. 22, 0:20, Jisheng Zhang wrote:
> On Mon, Nov 28, 2022 at 06:01:28PM +0200, Ilpo Järvinen wrote:
>> On Mon, 28 Nov 2022, Jisheng Zhang wrote:
>>
>>> On Mon, Nov 28, 2022 at 07:10:41AM +0100, Jiri Slaby wrote:
>>>> On 27. 11. 22, 14:24, Jisheng Zhang wrote:
>>>>> +static void bflb_uart_tx_chars(struct uart_port *port)
>>>>
>>>> Again:
>>>>
>>>> Are you unable to use the TX helper? If so:
>>>
>>> You know serial subsystem better than me, may I ask for more
>>> details? For example,
>>> Besides uart_xmit_advance(), do you expect other TX helpers? If yes,
>>> can you please list them?
>>
>> Please take on look on commit 8275b48b278096edc1e3ea5aa9cf946a10022f79.
>> The changes following that commit convert some drivers to use the tx
>> helper so you can look into them to see examples.
> 
> Thanks a lot for the hint. Will those tx helpers(uart_port_tx,
> uart_port_tx_limited etc.) be in v6.2-rc1? Or I need to patch
> based on Jiri's devel branch?

It's in tty-next and so in -next. You should base on either of those 
anyway ;). And yes, the plan is to have them in v6.2-rc1.

thanks,
-- 
js

Re: [PATCH v2 1/9] dt-bindings: serial: add documentation for Bouffalolab UART Driver

[Samuel Holland]

On 11/27/22 07:24, Jisheng Zhang wrote:
> Add bindings doc for Bouffalolab UART Driver
> 
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
>  .../bindings/serial/bouffalolab,uart.yaml     | 47 +++++++++++++++++++
>  1 file changed, 47 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml
> 
> diff --git a/Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml b/Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml
> new file mode 100644
> index 000000000000..a8293444ca31
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml
> @@ -0,0 +1,47 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/serial/bouffalolab,uart.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Bouffalolab UART Controller
> +
> +maintainers:
> +  - Jisheng Zhang <jszhang@kernel.org>
> +
> +allOf:
> +  - $ref: serial.yaml#
> +
> +properties:
> +  compatible:
> +    const: bouffalolab,bl808-uart
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1

There is also a reset control for this peripheral (in the GLB registers
at GLB_SWRST_S1A0).

And since you set additionalProperties, I believe you need to add the
DMA channel properties here as well.

Regards,
Samuel

> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - clocks
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +
> +    uart0: serial@30002000 {
> +        compatible = "bouffalolab,bl808-uart";
> +        reg = <0x30002000 0x1000>;
> +        interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
> +        clocks = <&xtal>;
> +    };
> +...

Re: [PATCH v2 3/9] riscv: add the Bouffalolab SoC family Kconfig option

[Samuel Holland]

On 11/27/22 07:24, Jisheng Zhang wrote:
> The Bouffalolab bl808 SoC contains three riscv CPUs, namely M0, D0 and
> LP. The D0 is 64bit RISC-V GC compatible, so can run linux.
> 
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  arch/riscv/Kconfig.socs | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 69774bb362d6..90256f44ed4a 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -1,5 +1,11 @@
>  menu "SoC selection"
>  
> +config SOC_BOUFFALOLAB

The options in this file are getting renamed soon, so this should be
named ARCH_BOUFFALOLAB. See

https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/

Regards,
Samuel

> +	bool "Bouffalolab SoCs"
> +	select SIFIVE_PLIC
> +	help
> +	  This enables support for Bouffalolab SoC platforms.
> +
>  config SOC_MICROCHIP_POLARFIRE
>  	bool "Microchip PolarFire SoCs"
>  	select MCHP_CLK_MPFS

Re: [PATCH v2 6/9] riscv: dts: bouffalolab: add the bl808 SoC base device tree

[Samuel Holland]

On 11/27/22 07:24, Jisheng Zhang wrote:
> Add a baisc dtsi for the bouffalolab bl808 SoC.
> 
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
>  arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 ++++++++++++++++++++++
>  1 file changed, 74 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> 
> diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> new file mode 100644
> index 000000000000..f4b170ccc32e
> --- /dev/null
> +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> @@ -0,0 +1,74 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +/*
> + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> +	compatible = "bouffalolab,bl808";
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	cpus {
> +		timebase-frequency = <1000000>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu@0 {
> +			compatible = "thead,c906", "riscv";
> +			device_type = "cpu";
> +			reg = <0>;
> +			d-cache-block-size = <64>;
> +			d-cache-sets = <256>;
> +			d-cache-size = <32768>;
> +			i-cache-block-size = <64>;
> +			i-cache-sets = <128>;
> +			i-cache-size = <32768>;
> +			mmu-type = "riscv,sv39";
> +			riscv,isa = "rv64imafdc";
> +
> +			cpu0_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#address-cells = <0>;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +	};
> +
> +	xtal: xtal-clk {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		/* This value must be overridden by the board */
> +		clock-frequency = <0>;
> +	};
> +
> +	soc {
> +		compatible = "simple-bus";
> +		ranges;
> +		interrupt-parent = <&plic>;
> +		dma-noncoherent;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +
> +		uart0: serial@30002000 {

It's unfortunate that the SDK/documentation calls this peripheral both
UART0 and UART3. I don't know if we can/should put the "M0" and "D0" bus
peripherals in the same DT; it seems like most of the "M0" peripherals
are not accessible from the C906. But if we did, this would conflict
with the other UART0.

> +			compatible = "bouffalolab,bl808-uart";
> +			reg = <0x30002000 0x1000>;
> +			interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&xtal>;

There's a clock controller with a mux and a gate between the crystal and
the UART. I'm not sure what the policy is about adding "fake" suppliers
before the real supplier has a binding defined.

Unfortunately, Bouffalolab threw everything and the kitchen sink into
the GLB register space, so that complicates defining the binding for the
clock/reset controller part.

> +			status = "disabled";
> +		};
> +
> +		plic: interrupt-controller@e0000000 {
> +			compatible = "thead,c900-plic";
> +			reg = <0xe0000000 0x4000000>;
> +			interrupts-extended = <&cpu0_intc 0xffffffff>,

The C906 PLIC has an M-mode context, so 0xffffffff is not correct. This
should reference the M-mode external interrupt.

> +					      <&cpu0_intc 9>;
> +			interrupt-controller;
> +			#address-cells = <0>;
> +			#interrupt-cells = <2>;
> +			riscv,ndev = <64>;

The SDK/documentation lists IRQ numbers up to BL808_IRQ_PDS == 82, so
this value should be at least that.

Regards,
Samuel

> +		};
> +	};
> +};

Re: [PATCH v2 7/9] riscv: dts: bouffalolab: add Sipeed M1s SoM and Dock devicetree

[Samuel Holland]

On 11/27/22 07:24, Jisheng Zhang wrote:
> Sipeed manufactures a M1s system-on-module and dock board, add basic
> support for them.
> 
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
>  arch/riscv/boot/dts/Makefile                  |  1 +
>  arch/riscv/boot/dts/bouffalolab/Makefile      |  2 ++
>  .../dts/bouffalolab/bl808-sipeed-m1s-dock.dts | 25 +++++++++++++++++++
>  .../dts/bouffalolab/bl808-sipeed-m1s.dtsi     | 21 ++++++++++++++++
>  4 files changed, 49 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/bouffalolab/Makefile
>  create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s-dock.dts
>  create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dtsi
> 
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index ff174996cdfd..b525467152b2 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -1,4 +1,5 @@
>  # SPDX-License-Identifier: GPL-2.0
> +subdir-y += bouffalolab
>  subdir-y += sifive
>  subdir-y += starfive
>  subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> diff --git a/arch/riscv/boot/dts/bouffalolab/Makefile b/arch/riscv/boot/dts/bouffalolab/Makefile
> new file mode 100644
> index 000000000000..5419964e892d
> --- /dev/null
> +++ b/arch/riscv/boot/dts/bouffalolab/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_SOC_BOUFFALOLAB) += bl808-sipeed-m1s-dock.dtb
> diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s-dock.dts b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s-dock.dts
> new file mode 100644
> index 000000000000..c6b4894a7b88
> --- /dev/null
> +++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s-dock.dts
> @@ -0,0 +1,25 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +/*
> + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
> + */
> +
> +/dts-v1/;
> +
> +#include "bl808-sipeed-m1s.dtsi"
> +
> +/ {
> +	model = "Sipeed M1s Dock";
> +	compatible = "sipeed,m1s-dock", "sipeed,m1s", "bouffalolab,bl808";
> +
> +	aliases {
> +		serial0 = &uart0;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:2000000n8";
> +	};
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dtsi
> new file mode 100644
> index 000000000000..5026de768534
> --- /dev/null
> +++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dtsi
> @@ -0,0 +1,21 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +/*
> + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
> + */
> +
> +/dts-v1/;
> +
> +#include "bl808.dtsi"
> +
> +/ {
> +	compatible = "sipeed,m1s", "bouffalolab,bl808";
> +
> +	memory@50000000 {
> +		device_type = "memory";
> +		reg = <0x50000000 0x04000000>;
> +	};

The PSRAM is part of the BL808, so this should go in the SoC .dtsi file.
(Unless I'm missing something and there are BL808 variants with
different amounts of memory. The PSRAM init code in the SDK does size
detection, so I suppose it is possible.)

Regards,
Samuel

> +};
> +
> +&xtal {
> +	clock-frequency = <40000000>;
> +};

Re: [PATCH v2 8/9] MAINTAINERS: riscv: add entry for Bouffalolab SoC

[Samuel Holland]

On 11/27/22 07:24, Jisheng Zhang wrote:
> Add Jisheng Zhang as Bouffalolab SoC maintainer.
> 
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
>  MAINTAINERS | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 00ff4a2949b8..a6b04249853c 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -17729,6 +17729,15 @@ F:	arch/riscv/
>  N:	riscv
>  K:	riscv
>  
> +RISC-V BOUFFALOLAB SOC SUPPORT
> +M:	Jisheng Zhang <jszhang@kernel.org>
> +L:	linux-riscv@lists.infradead.org
> +S:	Maintained
> +F:	Documentation/devicetree/bindings/riscv/bouffalolab.yaml
> +F:	Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml

I don't think you need to add YAML bindings here, because
get_maintainers.pl will find the maintainers listed inside the files.

Regards,
Samuel

> +F:	arch/riscv/boot/dts/bouffalolab/
> +F:	drivers/tty/serial/bflb_uart.c
> +
>  RISC-V MICROCHIP FPGA SUPPORT
>  M:	Conor Dooley <conor.dooley@microchip.com>
>  M:	Daire McNamara <daire.mcnamara@microchip.com>

Re: [PATCH v2 1/9] dt-bindings: serial: add documentation for Bouffalolab UART Driver

[Krzysztof Kozlowski]

On 27/11/2022 14:24, Jisheng Zhang wrote:
> Add bindings doc for Bouffalolab UART Driver
> 
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
>  .../bindings/serial/bouffalolab,uart.yaml     | 47 +++++++++++++++++++
>  1 file changed, 47 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml
> 
> diff --git a/Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml b/Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml
> new file mode 100644
> index 000000000000..a8293444ca31
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml

Name the file matching compatible, so bouffalolab,bl808-uart.yaml

> @@ -0,0 +1,47 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/serial/bouffalolab,uart.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Bouffalolab UART Controller
> +
> +maintainers:
> +  - Jisheng Zhang <jszhang@kernel.org>
> +
> +allOf:
> +  - $ref: serial.yaml#
> +
> +properties:
> +  compatible:
> +    const: bouffalolab,bl808-uart

Rob's comments from v1 are applicable. Either fix or respond to them.

> +
> +  reg:
> +    maxItems: 1
> +

Best regards,
Krzysztof

Re: [PATCH v2 4/9] dt-bindings: vendor-prefixes: add bouffalolab

[Krzysztof Kozlowski]

On 27/11/2022 14:24, Jisheng Zhang wrote:
> In the following commits, we will support bl808 SoC which is from
> Bouffalo Lab Technology (Nanjing) Co., Ltd.
> 
> Add bouffalolab vendor prefix binding.
> 
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
>  Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
>  1 file changed, 2 insertions(+)

Wrong order of commits. You cannot start using something before adding
its description. This should be the first patch in the set.

Best regards,
Krzysztof

Re: [PATCH v2 5/9] dt-bindings: riscv: Add bouffalolab bl808 board compatibles

[Krzysztof Kozlowski]

On 27/11/2022 14:24, Jisheng Zhang wrote:
> Several SoMs and boards are available that feature the Bouffalolab
> bl808 SoC. Document the compatible strings.
> 
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
>  .../bindings/riscv/bouffalolab.yaml           | 34 +++++++++++++++++++
>  1 file changed, 34 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/riscv/bouffalolab.yaml
> 
> diff --git a/Documentation/devicetree/bindings/riscv/bouffalolab.yaml b/Documentation/devicetree/bindings/riscv/bouffalolab.yaml
> new file mode 100644
> index 000000000000..91ca9dbdc798
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/riscv/bouffalolab.yaml
> @@ -0,0 +1,34 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/riscv/bouffalolab.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Bouffalo Lab Technology SoC-based boards
> +
> +maintainers:
> +  - Jisheng Zhang <jszhang@kernel.org>
> +
> +description:
> +  Bouffalo Lab Technology SoC-based boards
> +
> +properties:
> +  $nodename:
> +    const: '/'
> +  compatible:
> +    oneOf:
> +      - description: Sipeed M1s SoM:
> +        items:
> +          - const: sipeed,m1s
> +          - const: bouffalolab,bl808

I don't think that SoM is usable alone. It always needs a carrier, so
drop this entry.

Please run `make dt_binding_check` (see
Documentation/devicetree/bindings/writing-schema.rst for instructions).



Best regards,
Krzysztof

Re: [PATCH v2 5/9] dt-bindings: riscv: Add bouffalolab bl808 board compatibles

[Conor Dooley]

Hey Krzysztof,

On Thu, Dec 01, 2022 at 12:05:04PM +0100, Krzysztof Kozlowski wrote:
> On 27/11/2022 14:24, Jisheng Zhang wrote:
> > Several SoMs and boards are available that feature the Bouffalolab
> > bl808 SoC. Document the compatible strings.
> > 
> > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > ---
> >  .../bindings/riscv/bouffalolab.yaml           | 34 +++++++++++++++++++
> >  1 file changed, 34 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/riscv/bouffalolab.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/riscv/bouffalolab.yaml b/Documentation/devicetree/bindings/riscv/bouffalolab.yaml
> > new file mode 100644
> > index 000000000000..91ca9dbdc798
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/riscv/bouffalolab.yaml
> > @@ -0,0 +1,34 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/riscv/bouffalolab.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Bouffalo Lab Technology SoC-based boards
> > +
> > +maintainers:
> > +  - Jisheng Zhang <jszhang@kernel.org>
> > +
> > +description:
> > +  Bouffalo Lab Technology SoC-based boards
> > +
> > +properties:
> > +  $nodename:
> > +    const: '/'
> > +  compatible:
> > +    oneOf:
> > +      - description: Sipeed M1s SoM:
> > +        items:
> > +          - const: sipeed,m1s
> > +          - const: bouffalolab,bl808
> 
> I don't think that SoM is usable alone. It always needs a carrier, so
> drop this entry.

For my own information, if a SoM is not capable of functioning without a
carrier there is no merit in it having a compatible?
Does this also apply if there are multiple possible carriers from
different vendors?

Thanks,
Conor.

Re: [PATCH v2 5/9] dt-bindings: riscv: Add bouffalolab bl808 board compatibles

[Krzysztof Kozlowski]

On 01/12/2022 12:14, Conor Dooley wrote:
> Hey Krzysztof,
> 
> On Thu, Dec 01, 2022 at 12:05:04PM +0100, Krzysztof Kozlowski wrote:
>> On 27/11/2022 14:24, Jisheng Zhang wrote:
>>> Several SoMs and boards are available that feature the Bouffalolab
>>> bl808 SoC. Document the compatible strings.
>>>
>>> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
>>> ---
>>>  .../bindings/riscv/bouffalolab.yaml           | 34 +++++++++++++++++++
>>>  1 file changed, 34 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/riscv/bouffalolab.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/riscv/bouffalolab.yaml b/Documentation/devicetree/bindings/riscv/bouffalolab.yaml
>>> new file mode 100644
>>> index 000000000000..91ca9dbdc798
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/riscv/bouffalolab.yaml
>>> @@ -0,0 +1,34 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/riscv/bouffalolab.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Bouffalo Lab Technology SoC-based boards
>>> +
>>> +maintainers:
>>> +  - Jisheng Zhang <jszhang@kernel.org>
>>> +
>>> +description:
>>> +  Bouffalo Lab Technology SoC-based boards
>>> +
>>> +properties:
>>> +  $nodename:
>>> +    const: '/'
>>> +  compatible:
>>> +    oneOf:
>>> +      - description: Sipeed M1s SoM:
>>> +        items:
>>> +          - const: sipeed,m1s
>>> +          - const: bouffalolab,bl808
>>
>> I don't think that SoM is usable alone. It always needs a carrier, so
>> drop this entry.
> 
> For my own information, if a SoM is not capable of functioning without a
> carrier there is no merit in it having a compatible?
> Does this also apply if there are multiple possible carriers from
> different vendors?

Compatible makes sense anyway. There will be different boards using this
SoM (not only carriers, but final products) and they all will have
common piece - the SoM. It's the same for other SoM designs (e.g. for iMX).

Best regards,
Krzysztof

Re: [PATCH v2 0/9] riscv: add Bouffalolab bl808 support

[Palmer Dabbelt]

On Sun, 27 Nov 2022 05:24:39 PST (-0800), jszhang@kernel.org wrote:
> This series adds Bouffalolab uart driver and basic devicetrees for
> Bouffalolab bl808 SoC and Sipeed M1s dock board.
>
> It's too late for v6.2-rc1, but I hope I can catch up the v6.3-rc1
> window.
>
> I think I have addressed all review comments to v1, correct me if I
> missed anything.
>
> PS: this series assumes the "thead,c906" riscv cpu binding patch is
> merged(I see Conor has picked up it).
>
> Since v1:
>   - use FIELD_PREP and FIELD_GET macro
>   - rewrite bflb_uart_tx_chars()
>   - add vendor prefix for bouffalolab
>   - add dt binding for bl808 compatibles
>   - enable SOC_BOUFFALOLAB in defconfig
>   - collect Reviewed-by tag
>   - modify commit-msg as suggested
>
> Jisheng Zhang (9):
>   dt-bindings: serial: add documentation for Bouffalolab UART Driver
>   serial: bflb_uart: add Bouffalolab UART Driver
>   riscv: add the Bouffalolab SoC family Kconfig option
>   dt-bindings: vendor-prefixes: add bouffalolab
>   dt-bindings: riscv: Add bouffalolab bl808 board compatibles
>   riscv: dts: bouffalolab: add the bl808 SoC base device tree
>   riscv: dts: bouffalolab: add Sipeed M1s SoM and Dock devicetree
>   MAINTAINERS: riscv: add entry for Bouffalolab SoC
>   riscv: defconfig: enable BOUFFALOLAB SoC
>
>  .../bindings/riscv/bouffalolab.yaml           |  34 +
>  .../bindings/serial/bouffalolab,uart.yaml     |  47 ++
>  .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
>  MAINTAINERS                                   |   9 +
>  arch/riscv/Kconfig.socs                       |   6 +
>  arch/riscv/boot/dts/Makefile                  |   1 +
>  arch/riscv/boot/dts/bouffalolab/Makefile      |   2 +
>  .../dts/bouffalolab/bl808-sipeed-m1s-dock.dts |  25 +
>  .../dts/bouffalolab/bl808-sipeed-m1s.dtsi     |  21 +
>  arch/riscv/boot/dts/bouffalolab/bl808.dtsi    |  74 +++
>  arch/riscv/configs/defconfig                  |   1 +
>  drivers/tty/serial/Kconfig                    |  18 +
>  drivers/tty/serial/Makefile                   |   1 +
>  drivers/tty/serial/bflb_uart.c                | 610 ++++++++++++++++++
>  include/uapi/linux/serial_core.h              |   3 +
>  15 files changed, 854 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/riscv/bouffalolab.yaml
>  create mode 100644 Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml
>  create mode 100644 arch/riscv/boot/dts/bouffalolab/Makefile
>  create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s-dock.dts
>  create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dtsi
>  create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi
>  create mode 100644 drivers/tty/serial/bflb_uart.c

Acked-by: Palmer Dabbelt <palmer@rivosinc.com>

Re: [PATCH v2 7/9] riscv: dts: bouffalolab: add Sipeed M1s SoM and Dock devicetree

[Icenowy Zheng]

在 2022-11-30星期三的 01:25 -0600，Samuel Holland写道：
> On 11/27/22 07:24, Jisheng Zhang wrote:
> > Sipeed manufactures a M1s system-on-module and dock board, add
> > basic
> > support for them.
> > 
> > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > ---
> >  arch/riscv/boot/dts/Makefile                  |  1 +
> >  arch/riscv/boot/dts/bouffalolab/Makefile      |  2 ++
> >  .../dts/bouffalolab/bl808-sipeed-m1s-dock.dts | 25
> > +++++++++++++++++++
> >  .../dts/bouffalolab/bl808-sipeed-m1s.dtsi     | 21
> > ++++++++++++++++
> >  4 files changed, 49 insertions(+)
> >  create mode 100644 arch/riscv/boot/dts/bouffalolab/Makefile
> >  create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808-sipeed-
> > m1s-dock.dts
> >  create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808-sipeed-
> > m1s.dtsi
> > 
> > diff --git a/arch/riscv/boot/dts/Makefile
> > b/arch/riscv/boot/dts/Makefile
> > index ff174996cdfd..b525467152b2 100644
> > --- a/arch/riscv/boot/dts/Makefile
> > +++ b/arch/riscv/boot/dts/Makefile
> > @@ -1,4 +1,5 @@
> >  # SPDX-License-Identifier: GPL-2.0
> > +subdir-y += bouffalolab
> >  subdir-y += sifive
> >  subdir-y += starfive
> >  subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> > diff --git a/arch/riscv/boot/dts/bouffalolab/Makefile
> > b/arch/riscv/boot/dts/bouffalolab/Makefile
> > new file mode 100644
> > index 000000000000..5419964e892d
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/bouffalolab/Makefile
> > @@ -0,0 +1,2 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +dtb-$(CONFIG_SOC_BOUFFALOLAB) += bl808-sipeed-m1s-dock.dtb
> > diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s-
> > dock.dts b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s-
> > dock.dts
> > new file mode 100644
> > index 000000000000..c6b4894a7b88
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s-dock.dts
> > @@ -0,0 +1,25 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> > +/*
> > + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "bl808-sipeed-m1s.dtsi"
> > +
> > +/ {
> > +       model = "Sipeed M1s Dock";
> > +       compatible = "sipeed,m1s-dock", "sipeed,m1s",
> > "bouffalolab,bl808";
> > +
> > +       aliases {
> > +               serial0 = &uart0;
> > +       };
> > +
> > +       chosen {
> > +               stdout-path = "serial0:2000000n8";
> > +       };
> > +};
> > +
> > +&uart0 {
> > +       status = "okay";
> > +};
> > diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dtsi
> > b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dtsi
> > new file mode 100644
> > index 000000000000..5026de768534
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dtsi
> > @@ -0,0 +1,21 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> > +/*
> > + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "bl808.dtsi"
> > +
> > +/ {
> > +       compatible = "sipeed,m1s", "bouffalolab,bl808";
> > +
> > +       memory@50000000 {
> > +               device_type = "memory";
> > +               reg = <0x50000000 0x04000000>;
> > +       };
> 
> The PSRAM is part of the BL808, so this should go in the SoC .dtsi
> file.
> (Unless I'm missing something and there are BL808 variants with
> different amounts of memory. The PSRAM init code in the SDK does size
> detection, so I suppose it is possible.)

I think it really has variants.

> 
> Regards,
> Samuel
> 
> > +};
> > +
> > +&xtal {
> > +       clock-frequency = <40000000>;
> > +};
> 
> 
> _______________________________________________
> linux-riscv mailing list
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Re: [PATCH v2 6/9] riscv: dts: bouffalolab: add the bl808 SoC base device tree

[Icenowy Zheng]

在 2022-11-30星期三的 01:21 -0600，Samuel Holland写道：
> On 11/27/22 07:24, Jisheng Zhang wrote:
> > Add a baisc dtsi for the bouffalolab bl808 SoC.
> > 
> > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > ---
> >  arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74
> > ++++++++++++++++++++++
> >  1 file changed, 74 insertions(+)
> >  create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> > 
> > diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> > b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> > new file mode 100644
> > index 000000000000..f4b170ccc32e
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> > @@ -0,0 +1,74 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> > +/*
> > + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +
> > +/ {
> > +       compatible = "bouffalolab,bl808";
> > +       #address-cells = <1>;
> > +       #size-cells = <1>;
> > +
> > +       cpus {
> > +               timebase-frequency = <1000000>;
> > +               #address-cells = <1>;
> > +               #size-cells = <0>;
> > +
> > +               cpu0: cpu@0 {
> > +                       compatible = "thead,c906", "riscv";
> > +                       device_type = "cpu";
> > +                       reg = <0>;
> > +                       d-cache-block-size = <64>;
> > +                       d-cache-sets = <256>;
> > +                       d-cache-size = <32768>;
> > +                       i-cache-block-size = <64>;
> > +                       i-cache-sets = <128>;
> > +                       i-cache-size = <32768>;
> > +                       mmu-type = "riscv,sv39";
> > +                       riscv,isa = "rv64imafdc";
> > +
> > +                       cpu0_intc: interrupt-controller {
> > +                               compatible = "riscv,cpu-intc";
> > +                               interrupt-controller;
> > +                               #address-cells = <0>;
> > +                               #interrupt-cells = <1>;
> > +                       };
> > +               };
> > +       };
> > +
> > +       xtal: xtal-clk {
> > +               compatible = "fixed-clock";
> > +               #clock-cells = <0>;
> > +               /* This value must be overridden by the board */
> > +               clock-frequency = <0>;
> > +       };
> > +
> > +       soc {
> > +               compatible = "simple-bus";
> > +               ranges;
> > +               interrupt-parent = <&plic>;
> > +               dma-noncoherent;
> > +               #address-cells = <1>;
> > +               #size-cells = <1>;
> > +
> > +               uart0: serial@30002000 {
> 
> It's unfortunate that the SDK/documentation calls this peripheral
> both
> UART0 and UART3. I don't know if we can/should put the "M0" and "D0"
> bus
> peripherals in the same DT; it seems like most of the "M0"
> peripherals
> are not accessible from the C906. But if we did, this would conflict
> with the other UART0.

They're accessible but their interrupts are not, and I think this is
called d0_uart or uart3, but not uart0 at all.

> 
> > +                       compatible = "bouffalolab,bl808-uart";
> > +                       reg = <0x30002000 0x1000>;
> > +                       interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&xtal>;
> 
> There's a clock controller with a mux and a gate between the crystal
> and
> the UART. I'm not sure what the policy is about adding "fake"
> suppliers
> before the real supplier has a binding defined.
> 
> Unfortunately, Bouffalolab threw everything and the kitchen sink into
> the GLB register space, so that complicates defining the binding for
> the
> clock/reset controller part.
> 
> > +                       status = "disabled";
> > +               };
> > +
> > +               plic: interrupt-controller@e0000000 {
> > +                       compatible = "thead,c900-plic";

Using a single c900-plic here needs more discussion, I think.

> > +                       reg = <0xe0000000 0x4000000>;
> > +                       interrupts-extended = <&cpu0_intc
> > 0xffffffff>,
> 
> The C906 PLIC has an M-mode context, so 0xffffffff is not correct.
> This
> should reference the M-mode external interrupt.
> 
> > +                                             <&cpu0_intc 9>;
> > +                       interrupt-controller;
> > +                       #address-cells = <0>;
> > +                       #interrupt-cells = <2>;
> > +                       riscv,ndev = <64>;
> 
> The SDK/documentation lists IRQ numbers up to BL808_IRQ_PDS == 82, so
> this value should be at least that.
> 
> Regards,
> Samuel
> 
> > +               };
> > +       };
> > +};
> 
> 
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Re: [PATCH v2 6/9] riscv: dts: bouffalolab: add the bl808 SoC base device tree

[Conor Dooley]

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On Mon, Dec 05, 2022 at 04:17:59PM +0800, Icenowy Zheng wrote:
> 在 2022-11-30星期三的 01:21 -0600，Samuel Holland写道：
> > On 11/27/22 07:24, Jisheng Zhang wrote:
> > > Add a baisc dtsi for the bouffalolab bl808 SoC.
> > > 
> > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > > ---
> > >  arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74
> > > ++++++++++++++++++++++
> > >  1 file changed, 74 insertions(+)
> > >  create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> > > 
> > > diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> > > b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> > > new file mode 100644
> > > index 000000000000..f4b170ccc32e
> > > --- /dev/null
> > > +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> > > @@ -0,0 +1,74 @@
> > > +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> > > +/*
> > > + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
> > > + */
> > > +
> > > +#include <dt-bindings/interrupt-controller/irq.h>
> > > +
> > > +/ {
> > > +       compatible = "bouffalolab,bl808";
> > > +       #address-cells = <1>;
> > > +       #size-cells = <1>;
> > > +
> > > +       cpus {
> > > +               timebase-frequency = <1000000>;
> > > +               #address-cells = <1>;
> > > +               #size-cells = <0>;
> > > +
> > > +               cpu0: cpu@0 {
> > > +                       compatible = "thead,c906", "riscv";
> > > +                       device_type = "cpu";
> > > +                       reg = <0>;
> > > +                       d-cache-block-size = <64>;
> > > +                       d-cache-sets = <256>;
> > > +                       d-cache-size = <32768>;
> > > +                       i-cache-block-size = <64>;
> > > +                       i-cache-sets = <128>;
> > > +                       i-cache-size = <32768>;
> > > +                       mmu-type = "riscv,sv39";
> > > +                       riscv,isa = "rv64imafdc";
> > > +
> > > +                       cpu0_intc: interrupt-controller {
> > > +                               compatible = "riscv,cpu-intc";
> > > +                               interrupt-controller;
> > > +                               #address-cells = <0>;
> > > +                               #interrupt-cells = <1>;
> > > +                       };
> > > +               };
> > > +       };
> > > +
> > > +       xtal: xtal-clk {
> > > +               compatible = "fixed-clock";
> > > +               #clock-cells = <0>;
> > > +               /* This value must be overridden by the board */
> > > +               clock-frequency = <0>;
> > > +       };
> > > +
> > > +       soc {
> > > +               compatible = "simple-bus";
> > > +               ranges;
> > > +               interrupt-parent = <&plic>;
> > > +               dma-noncoherent;
> > > +               #address-cells = <1>;
> > > +               #size-cells = <1>;
> > > +
> > > +               uart0: serial@30002000 {
> > 
> > It's unfortunate that the SDK/documentation calls this peripheral
> > both
> > UART0 and UART3. I don't know if we can/should put the "M0" and "D0"
> > bus
> > peripherals in the same DT; it seems like most of the "M0"
> > peripherals
> > are not accessible from the C906. But if we did, this would conflict
> > with the other UART0.
> 
> They're accessible but their interrupts are not, and I think this is
> called d0_uart or uart3, but not uart0 at all.
> 
> > 
> > > +                       compatible = "bouffalolab,bl808-uart";
> > > +                       reg = <0x30002000 0x1000>;
> > > +                       interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
> > > +                       clocks = <&xtal>;
> > 
> > There's a clock controller with a mux and a gate between the crystal
> > and the UART. I'm not sure what the policy is about adding "fake"
> > suppliers before the real supplier has a binding defined.
> > 
> > Unfortunately, Bouffalolab threw everything and the kitchen sink into
> > the GLB register space, so that complicates defining the binding for
> > the clock/reset controller part.

I think it depends on how backwards/forwards compatible it's going to
be? If new kernel + old DT works then that's all that's "required",
right? Old kernel + new DT isn't going to work, but that's not required
AFAIU.

> > 
> > > +                       status = "disabled";
> > > +               };
> > > +
> > > +               plic: interrupt-controller@e0000000 {
> > > +                       compatible = "thead,c900-plic";
> 
> Using a single c900-plic here needs more discussion, I think.

Yah. Per the discussion on [1], I think I'd rather we avoided the single
c900-plic. Either a SoC-specific value, or "something" involving the
"openplic" naming is needed here.

Thanks,
Conor.

1 - https://lore.kernel.org/linux-riscv/20221121041757.418645-3-uwu@icenowy.me/

> > > +                       reg = <0xe0000000 0x4000000>;
> > > +                       interrupts-extended = <&cpu0_intc
> > > 0xffffffff>,
> > 
> > The C906 PLIC has an M-mode context, so 0xffffffff is not correct.
> > This
> > should reference the M-mode external interrupt.
> > 
> > > +                                             <&cpu0_intc 9>;
> > > +                       interrupt-controller;
> > > +                       #address-cells = <0>;
> > > +                       #interrupt-cells = <2>;
> > > +                       riscv,ndev = <64>;
> > 
> > The SDK/documentation lists IRQ numbers up to BL808_IRQ_PDS == 82, so
> > this value should be at least that.
> > 
> > Regards,
> > Samuel
> > 
> > > +               };
> > > +       };
> > > +};


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Re: [PATCH v2 6/9] riscv: dts: bouffalolab: add the bl808 SoC base device tree

[Michael Walle]

Hi,

> +		uart0: serial@30002000 {

According to the reference manual of the bl808, this is uart3. Can we also
use that name here?

> +			compatible = "bouffalolab,bl808-uart";
> +			reg = <0x30002000 0x1000>;
> +			interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&xtal>;

This is a shortcut and is likely to change in the future. The xtal
isn't really connected to the uart block, but instead there is a
clock mux and clock gate in between.

> +			status = "disabled";
> +		};

Thanks,
-michael