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From: Sunil V L <sunilvl@ventanamicro.com>
To: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org,
	linux-serial@vger.kernel.org
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	Len Brown <lenb@kernel.org>, Bjorn Helgaas <bhelgaas@google.com>,
	Anup Patel <anup@brainfault.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Jiri Slaby <jirislaby@kernel.org>,
	Conor Dooley <conor.dooley@microchip.com>,
	Andrew Jones <ajones@ventanamicro.com>,
	Atish Kumar Patra <atishp@rivosinc.com>,
	Haibo Xu <haibo1.xu@intel.com>,
	Sunil V L <sunilvl@ventanamicro.com>
Subject: [RFC PATCH v2 10/21] ACPI: RISC-V: Implement arch function to reorder irqchip probe entries
Date: Thu, 26 Oct 2023 01:53:33 +0530	[thread overview]
Message-ID: <20231025202344.581132-11-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com>

ACPI MADT entries for interrupt controllers don't have a way to describe
the hierarchy. However, the hierarchy is known to the architecture and
on RISC-V platforms, the MADT sub table types are ordered in the
incremental order from the root controller which is RINTC. So, add
architecture function for RISC-V to reorder the interrupt controller
probing as per the hierarchy as below.

RINTC->IMSIC->APLIC->PLIC

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
 drivers/acpi/riscv/Makefile |  2 +-
 drivers/acpi/riscv/irq.c    | 32 ++++++++++++++++++++++++++++++++
 2 files changed, 33 insertions(+), 1 deletion(-)
 create mode 100644 drivers/acpi/riscv/irq.c

diff --git a/drivers/acpi/riscv/Makefile b/drivers/acpi/riscv/Makefile
index 8b3b126e0b94..f80b3da230e9 100644
--- a/drivers/acpi/riscv/Makefile
+++ b/drivers/acpi/riscv/Makefile
@@ -1,2 +1,2 @@
 # SPDX-License-Identifier: GPL-2.0-only
-obj-y 	+= rhct.o
+obj-y 	+= rhct.o irq.o
diff --git a/drivers/acpi/riscv/irq.c b/drivers/acpi/riscv/irq.c
new file mode 100644
index 000000000000..36e0525b3235
--- /dev/null
+++ b/drivers/acpi/riscv/irq.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2023, Ventana Micro Systems Inc
+ *	Author: Sunil V L <sunilvl@ventanamicro.com>
+ *
+ */
+
+#include <linux/acpi.h>
+#include <linux/sort.h>
+
+static int irqchip_cmp_func(const void *in0, const void *in1)
+{
+	struct acpi_probe_entry *elem0 = (struct acpi_probe_entry *)in0;
+	struct acpi_probe_entry *elem1 = (struct acpi_probe_entry *)in1;
+
+	return (elem0->type > elem1->type) - (elem0->type < elem1->type);
+}
+
+/*
+ * RISC-V irqchips in MADT of ACPI spec are defined in the same order how
+ * they should be probed. Since IRQCHIP_ACPI_DECLARE doesn't define any
+ * order, this arch function will reorder the probe functions as per the
+ * required order for the architecture.
+ */
+void arch_sort_irqchip_probe(struct acpi_probe_entry *ap_head, int nr)
+{
+	struct acpi_probe_entry *ape = ap_head;
+
+	if (nr == 1 || !ACPI_COMPARE_NAMESEG(ACPI_SIG_MADT, ape->id))
+		return;
+	sort(ape, nr, sizeof(*ape), irqchip_cmp_func, NULL);
+}
-- 
2.39.2


  parent reply	other threads:[~2023-10-25 20:25 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-25 20:23 [RFC PATCH v2 00/21] RISC-V: ACPI: Add external interrupt controller support Sunil V L
2023-10-25 20:23 ` [RFC PATCH v2 01/21] arm64: PCI: Migrate ACPI related functions to pci-acpi.c Sunil V L
2023-10-26 16:31   ` Catalin Marinas
2023-10-25 20:23 ` [RFC PATCH v2 02/21] RISC-V: ACPI: Implement PCI related functionality Sunil V L
2023-10-25 20:23 ` [RFC PATCH v2 03/21] ACPI: Kconfig: Introduce new option to support deferred GSI probe Sunil V L
2023-10-25 20:23 ` [RFC PATCH v2 04/21] ACPI: irq: Add support for deferred probe in acpi_register_gsi() Sunil V L
2023-10-25 20:23 ` [RFC PATCH v2 05/21] pnp.h: Return -EPROBE_DEFER for disabled IRQ resource in pnp_irq() Sunil V L
2024-02-01 18:00   ` Rafael J. Wysocki
2024-02-02  8:48     ` Sunil V L
2023-10-25 20:23 ` [RFC PATCH v2 06/21] RISC-V: Kconfig: Select deferred GSI probe for ACPI systems Sunil V L
2023-10-26 17:04   ` Bjorn Helgaas
2023-10-25 20:23 ` [RFC PATCH v2 07/21] serial: 8250_pnp: Add support for deferred probe Sunil V L
2023-10-25 20:23 ` [RFC PATCH v2 08/21] ACPI: pci_irq: Avoid warning for deferred probe in acpi_pci_irq_enable() Sunil V L
2023-10-25 20:23 ` [RFC PATCH v2 09/21] ACPI: scan.c: Add weak arch specific function to reorder the IRQCHIP probe Sunil V L
2023-10-25 20:23 ` Sunil V L [this message]
2023-10-25 20:23 ` [RFC PATCH v2 11/21] PCI: MSI: Add helper function to set system wide MSI support Sunil V L
2023-10-30 14:28   ` Thomas Gleixner
2023-10-30 17:54     ` Sunil V L
2023-10-30 19:29       ` Thomas Gleixner
2023-10-31  2:00         ` Sunil V L
2023-10-25 20:23 ` [RFC PATCH v2 12/21] PCI: pci-acpi.c: Return correct value from pcibios_alloc_irq() Sunil V L
2023-10-25 20:23 ` [RFC PATCH v2 13/21] irqchip: riscv-intc: Add ACPI support for AIA Sunil V L
2023-10-26 16:51   ` Bjorn Helgaas
2023-10-27 11:29     ` Sunil V L
2023-10-27 11:54       ` Sunil V L
2023-10-27 17:45     ` Thomas Gleixner
2023-11-06 11:35       ` Marc Zyngier
2023-10-25 20:23 ` [RFC PATCH v2 14/21] irqchip: riscv-imsic: Add ACPI support Sunil V L
2023-10-25 20:23 ` [RFC PATCH v2 15/21] irqchip: riscv-aplic: " Sunil V L
2023-10-25 20:23 ` [RFC PATCH v2 16/21] irqchip: irq-sifive-plic: " Sunil V L
2023-10-25 20:23 ` [RFC PATCH v2 17/21] ACPI: bus: Add RINTC IRQ model for RISC-V Sunil V L
2023-10-25 20:23 ` [RFC PATCH v2 18/21] irqchip: riscv-intc: Set ACPI irqmodel Sunil V L
2023-10-25 20:23 ` [RFC PATCH v2 19/21] ACPI: bus: Add acpi_riscv_init function Sunil V L
2023-10-25 20:23 ` [RFC PATCH v2 20/21] ACPI: RISC-V: Create APLIC platform device Sunil V L
2023-10-25 20:23 ` [RFC PATCH v2 21/21] ACPI: RISC-V: Create PLIC " Sunil V L

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