Re: [PATCH v3 3/3] serial: sc16is7xx: add support for EXAR XR20M1172 UART

Jiri Slaby
2024-04-19T06:45:08Z

On 18. 04. 24, 19:06, Konstantin Pugin wrote:
> From: Konstantin Pugin <ria.freelander@gmail.com>
>
> XR20M1172 register set is mostly compatible with SC16IS762, but it has
> a support for additional division rates of UART with special DLD register.
> So, add handling this register by appropriate devicetree bindings.
>
> Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
> Signed-off-by: Konstantin Pugin <ria.freelander@gmail.com>
> ---
> drivers/tty/serial/sc16is7xx.c | 55 +++++++++++++++++++++++++++++++---
> 1 file changed, 51 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/tty/serial/sc16is7xx.c b/drivers/tty/serial/sc16is7xx.c
> index a300eebf1401..59376c637467 100644
> --- a/drivers/tty/serial/sc16is7xx.c
> +++ b/drivers/tty/serial/sc16is7xx.c
...
> @@ -218,6 +219,20 @@
> #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0)
> #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4)
>
> +/*
> + * Divisor Fractional Register bits (EXAR extension)
> + * EXAR hardware is mostly compatible with SC16IS7XX, but supports additional feature:
> + * 4x and 8x divisor, instead of default 16x. It has a special register to program it.
> + * Bits 0 to 3 is fractional divisor, it used to set value of last 16 bits of
> + * uartclk * (16 / divisor) / baud, in case of default it will be uartclk / baud.
> + * Bits 4 and 5 used as switches, and should not be set to 1 simultaneously.
> + */
> +
> +#define XR20M117X_DLD_16X 0
> +#define XR20M117X_DLD_DIV(m) ((m) & GENMASK(3, 0))

Again, why not set this up as a mask and use FIELD_PREP?

Could you stop submitting this many series in such a short time lapse?
It makes reviewing a major PITA.

--
js
suse labs