Re: [PATCH] serial: xilinx_uartps: read reg size from DTS

Greg Kroah-Hartman
2025-08-23T06:36:34Z

On Fri, Aug 22, 2025 at 11:58:14AM -0700, Harshit Shah wrote:
> Current implementation uses `CDNS_UART_REGISTER_SPACE(0x1000)`
> for request_mem_region() and ioremap() in cdns_uart_request_port() API.
>
> The cadence/xilinx IP has register space defined from offset 0x0 to 0x48.
> It also mentions that the register map is defined as [6:0]. So, the upper
> region may/maynot be used based on the IP integration.
>
> Fixes: 1f7055779001 ("arm64: dts: axiado: Add initial support for AX3000 SoC and eval board")
> In Axiado AX3000 SoC two UART instances are defined
> 0x100 apart. That is creating issue in some other instance due to overlap
> with addresses.
>
> Since, this address space is already being defined in the
> devicetree, use the same when requesting the register space.
>
> Acked-by: Michal Simek <michal.simek@amd.com>
> Signed-off-by: Harshit Shah <hshah@axiado.com>
> ---
> - Add fixes tag in commit msg

That fixes tag needs to go where the signed-off-by area is. See the
many examples on the lists and in the tree itself for specifics.

> - Link to v1: https://lore.kernel.org/r/20250819-xilinx-uartps-reg-size-v1-1-0fb7341023fb@axiado.com

Then why is this one not marked "v2"?

Can you fix this all up and send a v3?

thanks,

greg k-h