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Thu, 08 Jan 2026 04:26:07 -0800 (PST) From: Guodong Xu Subject: [PATCH v3 00/11] riscv: spacemit: Add SpacemiT K3 SoC and K3 Pico-ITX board Date: Thu, 08 Jan 2026 20:25:51 +0800 Message-Id: <20260108-k3-basic-dt-v3-0-ed99eb4c3ad3@riscstar.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAE+iX2kC/22PQU4DMQxFr1JlTVDidELCinsgFh47oRZqpyRhB Kp6d9x2A4jlt/We/j+ZXpqUbh43J9PKKl2Wg4ZwtzG0w8NrscKaDTiYPPho34KdsQtZHpY4T1v nos8pGyWOrVT5vNqeXzTvpI+lfV3lq79c//es3jqLjmGKlJkyPDXp1Ae2e1r25qJa4QcO8BsHx QPWUAOxqwn/4OdbtVbeP3TfuPUziher/70M3QtQyUPeZoY4JcZEcYYUY62VZs+ID4zOZ5WdvwH Ew//JNAEAAA== X-Change-ID: 20251216-k3-basic-dt-cd9540061989 To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yixun Lan , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Greg Kroah-Hartman , Jiri Slaby , Lubomir Rintel , Yangyu Chen Cc: Paul Walmsley , Conor Dooley , Heinrich Schuchardt , Kevin Meng Zhang , Anup Patel , Andrew Jones , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, spacemit@lists.linux.dev, linux-serial@vger.kernel.org, Guodong Xu , Krzysztof Kozlowski , Heinrich Schuchardt , Conor Dooley X-Mailer: b4 0.14.2 This series introduces basic support for the SpacemiT K3 SoC and the K3 Pico-ITX evaluation board. This series (starting from v2) also adds descriptions about ISA extensions mandated by the RVA23 Profile Version 1.0 into riscv/extensions.yaml. There are extensive discussions about how to handle these new extensions in v2. In v3, here is my best understading of what I think we have reached consensus on. The SpacemiT K3 is an SoC featuring 8 SpacemiT X100 RISC-V cores. The X100 is a 4-issue, out-of-order core compliant with the RVA23 profile, targeting high-performance scenarios. [1] The K3 Pico-ITX is an evaluation board built around the K3 SoC. >From an RVA23 profile compliance perspective, the X100 supports all mandatory extensions required by RVA23U64 and RVA23S64. Hi, Conor For the binding riscv/extensions.ymal, here's what changed in v3: 1. Dropped the patch of adding "supm" into extensions.yaml. At the same time, I will start another patchset which implements the strategy outlined by Conor in Link [2]. I understand there could be different opinions and anyway, let's move the discussion about "supm" into a patchset of its own. 2. Dropped the dependency checks for "sha" on "h", "shcounterenw", and 6 others. "sha" implies these extensions, and it should be allowed to be declared independently. 3. Enchanced the dependency check of "ziccamoa" on "a". Sepcifically, - added the dependecy check of "ziccamoa" on "zaamo" or on "a". - added the dependency check of "za64rs" on "zalrsc" or on "a". - added the dependency check of "ziccrse" on "zalrsc" or "a". The commit message of this patch is updated too, to better explain the relationship between "ziccamoa", "za64rs", "ziccrse" and "a". 4. Enhanced checking dependency of "b" and "zba", "zbb", "zbs", making the dependency check in both directions. Thank you for your review. Other Changes in v3 include: - Patch 1: Acked-by: Krzysztof Kozlowski - Patch 4: Acked-by: Krzysztof Kozlowski - Dropped Patch 5 "dt-bindings: serial: 8250: add SpacemiT K3 UART compatible" as it has been applied to tty-next. The entire series now rebased on top of tty-next (tty.git), which now merged with v6.19-rc3. Link: https://www.spacemit.com/en/spacemit-x100-core/ [1] Link: https://lore.kernel.org/lkml/20260101-legume-engraved-0fae8282cfbe@spud/ [2] Link to v2: https://lore.kernel.org/r/20251222-k3-basic-dt-v2-0-3af3f3cd0f8a@riscstar.com Changes in v2: - Patch 1: Fixed alphanumeric sorting order of compatible strings (swapped x100 and x60) as per Krzysztof's feedback. Update commit message with more information about X100 featurs per Yixun's feedback. - Patch 4: Fixed the order to keep things alphabetically. - Patch 6: Use "one blank space" between name and email address. - Patch 7 ~ 11: New patches. Add description of RVA23 mandatory extensions into riscv binding YAML file. - Patch 12 (Patch 7 in v1): Removed aliases node. Updated 'riscv,isa-extensions' with new extension strings available - Patch 13 (Patch 8 in v1): Updated the memory address to the hardware truth. Added aliases node in board dts. - Patch 1,2,3,5: Add Reviewed-by and Acked-by collected. Link to v1: https://lore.kernel.org/r/20251216-k3-basic-dt-v1-0-a0d256c9dc92@riscstar.com Signed-off-by: Guodong Xu --- Guodong Xu (11): dt-bindings: riscv: add SpacemiT X100 CPU compatible dt-bindings: timer: add SpacemiT K3 CLINT dt-bindings: interrupt-controller: add SpacemiT K3 APLIC dt-bindings: interrupt-controller: add SpacemiT K3 IMSIC dt-bindings: riscv: spacemit: add K3 and Pico-ITX board bindings dt-bindings: riscv: Add B ISA extension description dt-bindings: riscv: Add descriptions for Za64rs, Ziccamoa, Ziccif, and Zicclsm dt-bindings: riscv: Add Ssccptr, Sscounterenw, Sstvala, Sstvecd, Ssu64xl dt-bindings: riscv: Add Sha and its comprised extensions riscv: dts: spacemit: add initial device tree of SpacemiT K3 SoC riscv: dts: spacemit: add SpacemiT K3 Pico-ITX board device tree .../bindings/interrupt-controller/riscv,aplic.yaml | 1 + .../interrupt-controller/riscv,imsics.yaml | 1 + Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + .../devicetree/bindings/riscv/extensions.yaml | 169 +++++++ .../devicetree/bindings/riscv/spacemit.yaml | 4 + .../devicetree/bindings/timer/sifive,clint.yaml | 1 + arch/riscv/boot/dts/spacemit/Makefile | 1 + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 38 ++ arch/riscv/boot/dts/spacemit/k3.dtsi | 548 +++++++++++++++++++++ 9 files changed, 764 insertions(+) --- base-commit: 322fc12949d2658da8c6b2866fffcb1daa7da019 change-id: 20251216-k3-basic-dt-cd9540061989 Best regards, -- Guodong Xu